PMUACR_EL1 Performance Monitors User Access Control Register when FEAT_PMUv3p9 is implemented and FEAT_AA64 is implemented Enables or disables EL0 access to specfic Performance Monitors. PMU PMUACR_EL1 is a 64-bit register. 63 33 63:33 Reserved, RES0. F0 32 32 0 EL0 accesses to PMICNTR_EL0 enable. With PMUSERENR_EL0.UEN and PMUSERENR_EL0.IR, controls EL0 accesses to PMICNTR_EL0. The controls associated with PMICNTR_EL0 that are accessible at EL0 are PMCNTENSET_EL0.F0, PMCNTENCLR_EL0.F0, PMOVSSET_EL0.F0, and PMOVSCLR_EL0.F0. This field is ignored by the PE when any of the following are true: EL1 is using AArch32. PMUSERENR_EL0.UEN is 0. The access generates an exception. 0b0 If the Effective value of PMUSERENR_EL0.UEN is 1, then EL0 accesses to PMICNTR_EL0 and associated controls are RAZ/WI, and permitted EL0 writes to PMZR_EL0.F0 are ignored. 0b1 If the Effective value of PMUSERENR_EL0.UEN is 1, then EL0 accesses to PMICNTR_EL0 and associated controls are either read-only or read/write, depending on the value of PMUSERENR_EL0.IR. AU When FEAT_PMUv3_ICNTR is implemented 32 32 32 Reserved, RES0. Otherwise C 31 31 31 EL0 accesses to PMCCNTR_EL0 enable. With PMUSERENR_EL0.EN, PMUSERENR_EL0.UEN, and PMUSERENR_EL0.CR, controls EL0 accesses to PMCCNTR_EL0. The controls associated with PMCCNTR_EL0 that are accessible at EL0 are PMCNTENSET_EL0.C, PMCNTENCLR_EL0.C, PMOVSSET_EL0.C, and PMOVSCLR_EL0.C. This field is ignored by the PE when any of the following are true: EL1 is using AArch32. PMUSERENR_EL0.UEN is 0. The access generates an exception. 0b0 If the Effective value of PMUSERENR_EL0.UEN is 1, then EL0 accesses to PMCCNTR_EL0 and associated controls are RAZ/WI, and permitted EL0 writes to PMZR_EL0.C are ignored. 0b1 If the Effective value of PMUSERENR_EL0.UEN is 1, then EL0 accesses to PMCCNTR_EL0 and associated controls are either read-only or read/write, depending on the value of PMUSERENR_EL0.CR. AU P<m> 30 0 30:0 EL0 accesses to PMEVCNTR<m>_EL0 enable. With PMUSERENR_EL0.EN, PMUSERENR_EL0.UEN, and PMUSERENR_EL0.ER, controls EL0 accesses to PMEVCNTR<m>_EL0. The controls associated with PMEVCNTR<m>_EL0 that are accessible at EL0 are PMCNTENSET_EL0.P<m>, PMCNTENCLR_EL0.P<m>, PMOVSSET_EL0.P<m>, and PMOVSCLR_EL0.P<m>. This field is ignored by the PE when any of the following are true: EL1 is using AArch32. PMUSERENR_EL0.UEN is 0. The access generates an exception. 30 0 0b0 If the Effective value of PMUSERENR_EL0.UEN is 1, then EL0 accesses to PMEVCNTR<m>_EL0 and associated controls are RAZ/WI, and permitted EL0 writes to PMZR_EL0.P<m> are ignored. 0b1 If the Effective value of PMUSERENR_EL0.UEN is 1, then EL0 accesses to PMEVCNTR<m>_EL0 and associated controls are either read-only or read/write, depending on the value of PMUSERENR_EL0.ER. AU When m >= GetNumEventCountersAccessible() RAZ/WI RW MRS <Xt>, PMUACR_EL1 if !(IsFeatureImplemented(FEAT_PMUv3p9) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nPMUACR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMUACR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMUACR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMUACR_EL1(); end; MSR PMUACR_EL1, <Xt> if !(IsFeatureImplemented(FEAT_PMUv3p9) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nPMUACR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMUACR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMUACR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMUACR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel