PMUSERENR_EL0 Performance Monitors User Enable Register when FEAT_PMUv3 is implemented and FEAT_AA64 is implemented PMUSERENR Architectural AArch32 31 0 31 0 31 0 31 0 Enables or disables EL0 access to the Performance Monitors. PMU PMUSERENR_EL0 is a 64-bit register. 63 7 63:7 Reserved, RES0. TID 6 6 0 Trap ID registers. Traps EL0 read access to common event identification registers. In AArch64 state, the register accesses affected by this control are: MRS reads of PMCEID0_EL0 and PMCEID1_EL0. In AArch32 state, the register accesses affected by this control are: MRC reads of PMCEID0, PMCEID1, PMCEID2, and PMCEID3. When trapped, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS reads are reported using EC syndrome value 0x18. AArch32 MRC reads are reported using EC syndrome value 0x03. 0b0 Accesses to PMCEID<n>_EL0 and PMCEID<n> are not trapped by this mechanism. 0b1 EL0 read accesses to PMCEID<n>_EL0 and PMCEID<n> are trapped. AU When FEAT_PMUv3p9 is implemented 6 6 6 Reserved, RES0. Otherwise IR 5 5 0 Instruction counter Read-only. When PMUSERENR_EL0.UEN is 1, controls whether EL0 writes to instruction counter are ignored. The controls associated with PMICNTR_EL0 that are accessible at EL0 are PMCNTENSET_EL0.F0, PMCNTENCLR_EL0.F0, PMOVSSET_EL0.F0, and PMOVSCLR_EL0.F0. Ignored writes are not trapped and do not generate an exception. This field is ignored by the PE when any of the following are true: PMUSERENR_EL0.UEN is 0. The access generates an exception. 0b0 EL0 accesses are not affected by this mechanism. 0b1 If the Effective value of PMUSERENR_EL0.UEN is 1, then all of the following apply at EL0: Writes to PMICNTR_EL0 are ignored. The controls associated with instruction counter are RAZ/WI. Writes to PMZR_EL0.F0 are ignored. AU When FEAT_PMUv3_ICNTR is implemented 5 5 5 Reserved, RES0. Otherwise UEN 4 4 0 User Enable, with access controlled by PMUACR_EL1. Enables EL0 read/write access to PMU registers, other than PMCR_EL0. In AArch64 state, the register accesses affected by this control are: MRS or MSR accesses to the following registers: PMCCFILTR_EL0, PMCCNTR_EL0, PMCNTENCLR_EL0, PMCNTENSET_EL0, PMEVCNTR<n>_EL0, PMEVTYPER<n>_EL0, PMOVSCLR_EL0, PMOVSSET_EL0, PMSELR_EL0, PMXEVCNTR_EL0, and PMXEVTYPER_EL0. If FEAT_PMUv3_ICNTR is implemented, PMICFILTR_EL0 and PMICNTR_EL0. MRS reads of PMCEID0_EL0 and PMCEID1_EL0. MSR writes to PMSWINC_EL0 and PMZR_EL0. In AArch32 state, the register accesses affected by this control are: MRC or MCR accesses to PMCCFILTR, PMCCNTR, PMCNTENCLR, PMCNTENSET, PMEVCNTR<n>, PMEVTYPER<n>, PMOVSR, PMOVSSET, PMSELR, PMXEVCNTR, and PMXEVTYPER. MRC reads of PMCEID0, PMCEID1, PMCEID2, and PMCEID3. MCR writes to PMSWINC. MRRC or MCRR accesses to PMCCNTR. When trapped, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS and MSR accesses are reported using EC syndrome value 0x18. AArch32 MRC and MCR accesses are reported using EC syndrome value 0x03. AArch32 MRRC and MCRR accesses are reported using EC syndrome value 0x04. This field is ignored by the PE and treated as zero when EL1 is using AArch32. 0b0 If FEAT_PMUv3_ICNTR is implemented, then EL0 accesses to PMICFILTR_EL0 and PMICNTR_EL0 are trapped. EL0 accesses to the other specified PMU registers, PMCR_EL0, and PMCR are trapped, unless enabled by PMUSERENR_EL0.{ER,CR,SW,EN}. 0b1 EL0 accesses to the specified PMU registers are enabled, unless trapped by another control. The behavior of permitted accesses is controlled by PMUSERENR_EL0.{ IR, ER,CR,SW} and PMUACR_EL1. EL0 accesses to PMCR_EL0 and PMCR are trapped. AU When FEAT_PMUv3p9 is implemented 4 4 4 Reserved, RES0. Otherwise ER 3 3 0 Event counters Read enable or Read-only. When PMUSERENR_EL0.{UEN,EN} is {0,0}, PMUSERENR_EL0.ER enables EL0 reads of the event counters and EL0 reads and writes of the select register. When PMUSERENR_EL0.UEN is 1, EL0 reads of the event counters and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.ER controls the behavior of EL0 writes to the event counters and PMZR_EL0. In AArch64 state, the register accesses affected by this control are: When PMUSERENR_EL0.{UEN,EN} is {0,0}: MRS reads of PMEVCNTR<n>_EL0 and PMXEVCNTR_EL0. MRS and MSR accesses to PMSELR_EL0. When PMUSERENR_EL0.UEN is 1, MSR writes to PMZR_EL0.P<n>, PMEVCNTR<n>_EL0, and PMXEVCNTR_EL0. In AArch32 state, the register accesses affected by this control are: When PMUSERENR_EL0.{UEN,EN} is {0,0}: MRC reads of PMEVCNTR<n> and PMXEVCNTR. MRC and MCR accesses to PMSELR. When PMUSERENR_EL0.UEN is 1, MCR writes to PMEVCNTR<n> and PMXEVCNTR. When disabled, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS and MSR accesses are reported using EC syndrome value 0x18. AArch32 MRC and MCR accesses are reported using EC syndrome value 0x03. Ignored writes are not trapped and do not generate an exception. This field is ignored by the PE when PMUSERENR_EL0.{UEN,EN} == {0,1}. 0b0 When PMUSERENR_EL0.UEN == 0, EL0 reads of the event counters and EL0 reads and writes of the select register are disabled, unless enabled by PMUSERENR_EL0.EN. When PMUSERENR_EL0.UEN == 1, permitted EL0 writes are not affected by this mechanism. 0b1 When PMUSERENR_EL0.UEN == 0, EL0 reads of the event counters and EL0 reads and writes of the select register are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1, permitted EL0 writes to the event counters and PMZR_EL0.P[30:0] are ignored. AU When FEAT_PMUv3p9 is implemented ER 3 3 0 Event counters Read enable. When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.ER enables EL0 reads of the event counters and EL0 reads and writes of the select register. In AArch64 state, the register accesses affected by this control are: MRS reads of PMEVCNTR<n>_EL0 and PMXEVCNTR_EL0. MRS and MSR accesses to PMSELR_EL0. In AArch32 state, the register accesses affected by this control are: MRC reads of PMEVCNTR<n> and PMXEVCNTR. MRC and MCR accesses to PMSELR. When disabled, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS and MSR accesses are reported using EC syndrome value 0x18. AArch32 MRC and MCR accesses are reported using EC syndrome value 0x03. This field is ignored by the PE when PMUSERENR_EL0.EN == 1. 0b0 EL0 reads of the event counters and EL0 reads and writes of the select register are disabled, unless enabled by PMUSERENR_EL0.EN. 0b1 EL0 reads of the event counters and EL0 reads and writes of the select register are enabled, unless trapped by another control. AU Otherwise CR 2 2 0 Cycle counter Read enable or Read-only. When PMUSERENR_EL0.{UEN,EN} is {0,0}, PMUSERENR_EL0.CR enables EL0 reads of the cycle counter. When PMUSERENR_EL0.UEN is 1, EL0 reads of the cycle counter and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.CR controls the behavior of EL0 writes to the cycle counter and PMZR_EL0. In AArch64 state, the register accesses affected by this control are: When PMUSERENR_EL0.{UEN,EN} is {0,0}, MRS reads of PMCCNTR_EL0. When PMUSERENR_EL0.UEN is 1, MSR writes to PMZR_EL0.C and PMCCNTR_EL0. In AArch32 state, the register accesses affected by this control are: When PMUSERENR_EL0.{UEN,EN} is {0,0}: MRC reads of PMCCNTR. MRRC reads of PMCCNTR. When PMUSERENR_EL0.UEN is 1: MCR writes to PMCCNTR. MCRR writes to PMCCNTR. When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS reads are reported using EC syndrome value 0x18. AArch32 MRC reads are reported using EC syndrome value 0x03. AArch32 MRRC reads are reported using EC syndrome value 0x04. Ignored writes are not trapped and do not generate an exception. This field is ignored by the PE when PMUSERENR_EL0.{UEN,EN} == {0,1}. 0b0 When PMUSERENR_EL0.UEN == 0, EL0 reads of the cycle counter are disabled, unless enabled by PMUSERENR_EL0.EN. When PMUSERENR_EL0.UEN == 1, permitted EL0 writes are not affected by this mechanism. 0b1 When PMUSERENR_EL0.UEN == 0, EL0 reads of the cycle counter are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1, permitted EL0 writes to the cycle counter and PMZR_EL0.C are ignored. AU When FEAT_PMUv3p9 is implemented CR 2 2 0 Cycle counter Read enable. When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.CR enables EL0 reads of the cycle counter. In AArch64 state, the register accesses affected by this control are: MRS reads of PMCCNTR_EL0. In AArch32 state, the register accesses affected by this control are: MRC reads of PMCCNTR. MRRC reads of PMCCNTR. When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS reads are reported using EC syndrome value 0x18. AArch32 MRC reads are reported using EC syndrome value 0x03. AArch32 MRRC reads are reported using EC syndrome value 0x04. This field is ignored by the PE when PMUSERENR_EL0.EN == 1. 0b0 EL0 reads of the cycle counter are disabled, unless enabled by PMUSERENR_EL0.EN. 0b1 EL0 reads of the cycle counter are enabled, unless trapped by another control. AU Otherwise SW 1 1 0 Software increment register Write enable. When PMUSERENR_EL0.UEN is 0, PMUSERENR_EL0.SW enables EL0 writes to the Software increment register. When PMUSERENR_EL0.UEN is 1, EL0 writes to the Software increment register are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.SW controls the behavior of EL0 writes to the Software increment register. In AArch64 state, the register accesses affected by this control are: MSR writes to PMSWINC_EL0. In AArch32 state, the register accesses affected by this control are: MCR writes to PMSWINC. When disabled, writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MSR writes are reported using EC syndrome value 0x18. AArch32 MCR writes are reported using EC syndrome value 0x03. This field is ignored by the PE when PMUSERENR_EL0.{UEN,EN} == {0,1}. 0b0 When PMUSERENR_EL0.UEN == 0, EL0 writes to the Software increment register are disabled, unless enabled by PMUSERENR_EL0.EN. When PMUSERENR_EL0.UEN == 1, permitted EL0 writes are not affected by this mechanism. 0b1 When PMUSERENR_EL0.UEN == 0, EL0 writes to the Software increment register are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1, permitted EL0 writes to the Software increment register ignore the value of PMUACR_EL1. AU When FEAT_PMUv3p9 is implemented SW 1 1 0 Software increment register Write enable. When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.SW enables EL0 writes to the Software increment register. In AArch64 state, the register accesses affected by this control are: MSR writes to PMSWINC_EL0. In AArch32 state, the register accesses affected by this control are: MCR writes to PMSWINC. When disabled, writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MSR writes are reported using EC syndrome value 0x18. AArch32 MCR writes are reported using EC syndrome value 0x03. This field is ignored by the PE when PMUSERENR_EL0.EN == 1. 0b0 EL0 writes to the Software increment register are disabled, unless enabled by PMUSERENR_EL0.EN. 0b1 EL0 writes to the Software increment register are enabled, unless trapped by another control. AU Otherwise EN 0 0 0 Enable. Enables EL0 read/write access to PMU registers, other than the instruction counter. In AArch64 state, the register accesses affected by this control are: MRS or MSR accesses to PMCCFILTR_EL0, PMCCNTR_EL0, PMCNTENCLR_EL0, PMCNTENSET_EL0, PMCR_EL0, PMEVCNTR<n>_EL0, PMEVTYPER<n>_EL0, PMOVSCLR_EL0, PMOVSSET_EL0, PMSELR_EL0, PMXEVCNTR_EL0, and PMXEVTYPER_EL0. MRS reads of PMCEID0_EL0 and PMCEID1_EL0. MSR writes to the following registers: PMSWINC_EL0. If FEAT_PMUv3p9 is implemented, PMZR_EL0. When FEAT_PMUv3_ICNTR is implemented, this field does not affect MRS and MSR accesses to PMICNTR_EL0 and PMICFILTR_EL0.In AArch32 state, the register accesses affected by this control are: MRC or MCR accesses to PMCCFILTR, PMCCNTR, PMCNTENCLR, PMCNTENSET, PMCR, PMEVCNTR<n>, PMEVTYPER<n>, PMOVSR, PMOVSSET, PMSELR, PMXEVCNTR, and PMXEVTYPER. MRC reads of the following registers: PMCEID0 and PMCEID1. If FEAT_PMUv3p1 is implemented, PMCEID2 and PMCEID3. MCR writes to PMSWINC. MRRC or MCRR accesses to PMCCNTR. When trapped, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and: AArch64 MRS and MSR accesses are reported using EC syndrome value 0x18. AArch32 MRC and MCR accesses are reported using EC syndrome value 0x03. AArch32 MRRC and MCRR accesses are reported using EC syndrome value 0x04. This field is ignored by the PE when FEAT_PMUv3p9 is implemented and PMUSERENR_EL0.UEN == 1. 0b0 EL0 accesses to the specified PMU System registers are trapped, unless enabled by PMUSERENR_EL0.{UEN,ER,CR,SW}. 0b1 EL0 accesses to the specified PMU System registers are enabled, unless trapped by another control. AU MRS <Xt>, PMUSERENR_EL0 if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMUSERENR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMUSERENR_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMUSERENR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMUSERENR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMUSERENR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMUSERENR_EL0(); end; MSR PMUSERENR_EL0, <Xt> if !(IsFeatureImplemented(FEAT_PMUv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMUSERENR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMUSERENR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMUSERENR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMUSERENR_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel