POR_EL2 Permission Overlay Register 2 (EL2) when FEAT_S1POE is implemented and FEAT_AA64 is implemented Stage 1 Permission Overlay Register for privileged access of the EL2 or EL2&0 translation regime. Memory If EL2 is not implemented, this register is RES0 from EL3. POR_EL2 is a 64-bit register. Perm<m> 63 0 63:0 Perm Represents stage 1 Overlay Permissions. If FEAT_D128 is implemented and VMSAv9-128 is in use, then fields Perm[8] to Perm[15] are used for POIndex values 8 to 15. Otherwise, the fields Perm[8] to Perm[15] are RES0. This field is not permitted to be cached in a TLB. When the stage 1 Overlay mechanism is disabled, this field is IGNORED. 15 0 0b0000 No access. 0b0001 Read. 0b0010 Execute. 0b0011 Read, Execute. 0b0100 Write. 0b0101 Write, Read. 0b0110 Write, Execute. 0b0111 Read, Write, Execute. 0b1xxx Reserved - treated as No access AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name POR_EL2 or POR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, POR_EL2 if !(IsFeatureImplemented(FEAT_S1POE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = POR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = POR_EL2(); end; MSR POR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_S1POE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else POR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then POR_EL2() = X{64}(t); end; MRS <Xt>, POR_EL1 if !(IsFeatureImplemented(FEAT_S1POE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().nPOR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x2A8); else X{64}(t) = POR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = POR_EL2(); else X{64}(t) = POR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = POR_EL1(); end; MSR POR_EL1, <Xt> if !(IsFeatureImplemented(FEAT_S1POE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().nPOR_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x2A8) = X{64}(t); else POR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then POR_EL2() = X{64}(t); else POR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then POR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel