RCWMASK_EL1 Read Check Write Instruction Mask (EL1) when FEAT_THE is implemented and FEAT_AA64 is implemented Contains the mask used by RCW instructions. Memory RCWMASK_EL1 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64]. RCWMASK_EL1 is a: 128-bit register when FEAT_D128 is implemented 64-bit register otherwise When FEAT_D128 is implemented RCWMASK 127 0 127:0 Mask used to decide which bit-fields are writable to the 128-bit Descriptor by RCW or RCWS instructions. If RCWMASK_EL1 is indirectly read by 128-bit variants of RCW or RCWS instructions: The Effective value of RCWMASK[n] is the same as RCWMASK_EL1[n], except as follows: If n >= 17, and n <= 55, the Effective value of RCWMASK[n] is the same as RCWMASK_EL1[16]. If n is in {126:125, 120:119, 114, 107:101, 90:56, 1:0}, the Effective value of RCWMASK[n] is 0. If n >= 121, n <= 124, and FEAT_S1POE is not implemented, the Effective value of RCWMASK[n] is 0. If FEAT_MEC is not implemented, the Effective value of RCWMASK[108] is 0. If RCWMASK_EL1 is indirectly read by 64-bit variants of RCW or RCWS instructions: The Effective value of RCWMASK[n] is the same as RCWMASK_EL1[n], except as follows: If n >= 18, and n <= 49, the Effective value of RCWMASK[n] is the same as RCWMASK_EL1[17]. RCWMASK_EL1 register bits {126:125, 120:119, 114, 107:101, 90:64, 52, 49:18, 0} are RES0. If FEAT_S1POE is not implemented, RCWMASK_EL1 register bits {124:121} are RES0. If FEAT_MEC is not implemented, RCWMASK_EL1[108] is RES0. AU RCWMASK 63 0 63:0 Mask used to decide which bit-fields are writable to the 64-bit Descriptor by RCW or RCWS Instructions. The Effective value of RCWMASK[n] is the same as RCWMASK_EL1[n], except as follows: If n >= 18, and n <= 49, the Effective value of RCWMASK[n] is the same as RCWMASK_EL1[17]. RCWMASK_EL1 register bits {52, 49:18, 0} are RES0. AU When FEAT_D128 is implemented MRS <Xt>, RCWMASK_EL1 if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().nRCWMASK_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = RCWMASK_EL1()[63:0]; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = RCWMASK_EL1()[63:0]; end; elsif PSTATE.EL == EL3 then X{64}(t) = RCWMASK_EL1()[63:0]; end; MSR RCWMASK_EL1, <Xt> if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().nRCWMASK_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else RCWMASK_EL1()[63:0] = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else RCWMASK_EL1()[63:0] = X{64}(t); end; elsif PSTATE.EL == EL3 then RCWMASK_EL1()[63:0] = X{64}(t); end; MRRS <Xt>, <Xt+1>, RCWMASK_EL1 When FEAT_D128 is implemented if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().nRCWMASK_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().D128En == '0') then AArch64_SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else X{128}(t, t2) = RCWMASK_EL1()[127:0]; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else X{128}(t, t2) = RCWMASK_EL1()[127:0]; end; elsif PSTATE.EL == EL3 then X{128}(t, t2) = RCWMASK_EL1()[127:0]; end; MSRR RCWMASK_EL1, <Xt>, <Xt+1> When FEAT_D128 is implemented if !(IsFeatureImplemented(FEAT_THE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().nRCWMASK_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().D128En == '0') then AArch64_SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else RCWMASK_EL1()[127:0] = X{128}(t, t2); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().RCWMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().D128En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().RCWMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; elsif HaveEL(EL3) && SCR_EL3().D128En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x14); end; else RCWMASK_EL1()[127:0] = X{128}(t, t2); end; elsif PSTATE.EL == EL3 then RCWMASK_EL1()[127:0] = X{128}(t, t2); end; 2026-03-26 20:27:25 2026-03_rel