Accelerator Data Auxiliary Control Masking Register (EL1) Auxiliary Control Masking Register (EL2) Auxiliary Control Register (EL1) Auxiliary Control Register (EL2) Auxiliary Control Register (EL3) Auxiliary Fault Status Register 0 (EL1) Auxiliary Fault Status Register 0 (EL2) Auxiliary Fault Status Register 0 (EL3) Auxiliary Fault Status Register 1 (EL1) Auxiliary Fault Status Register 1 (EL2) Auxiliary Fault Status Register 1 (EL3) Auxiliary ID Register All Interrupt Mask Bit Extended Auxiliary Memory Attribute Indirection Register (EL1) Extended Auxiliary Memory Attribute Indirection Register (EL2) Extended Auxiliary Memory Attribute Indirection Register (EL3) Auxiliary Memory Attribute Indirection Register (EL1) Auxiliary Memory Attribute Indirection Register (EL2) Auxiliary Memory Attribute Indirection Register (EL3) Activity Monitors Configuration Register Activity Monitors Counter Group 1 Identification Register Activity Monitors Counter Group Configuration Register Activity Monitors Count Enable Clear Register 0 Activity Monitors Count Enable Clear Register 1 Activity Monitors Count Enable Set Register 0 Activity Monitors Count Enable Set Register 1 Activity Monitors Control Register Activity Monitors Event Counter Registers 0 Activity Monitors Event Counter Registers 1 Activity Monitors Event Counter Virtual Offset Registers 0 Activity Monitors Event Counter Virtual Offset Registers 1 Activity Monitors Event Type Registers 0 Activity Monitors Event Type Registers 1 Activity Monitors User Enable Register Pointer Authentication Key A for Data (bits[127:64]) Pointer Authentication Key A for Data (bits[63:0]) Pointer Authentication Key B for Data (bits[127:64]) Pointer Authentication Key B for Data (bits[63:0]) Pointer Authentication Key A for Code (bits[127:64]) Pointer Authentication Key A for Code (bits[63:0]) Pointer Authentication Key A for Instruction (bits[127:64]) Pointer Authentication Key A for Instruction (bits[63:0]) Pointer Authentication Key B for Instruction (bits[127:64]) Pointer Authentication Key B for Instruction (bits[63:0]) Branch Record Buffer Control Register (EL1) Branch Record Buffer Control Register (EL2) Branch Record Buffer Function Control Register Branch Record Buffer ID0 Register Branch Record Buffer Information Register <n> Branch Record Buffer Information Injection Register Branch Record Buffer Source Address Register <n> Branch Record Buffer Source Address Injection Register Branch Record Buffer Target Address Register <n> Branch Record Buffer Target Address Injection Register Branch Record Buffer Timestamp Register Current Cache Size ID Register 2 Current Cache Size ID Register Cache Level ID Register Counter-timer Frequency Register Counter-timer Hypervisor Control Register Counter-timer Secure Physical Timer Control Register (EL2) Counter-timer Secure Physical Timer CompareValue Register (EL2) Counter-timer Secure Physical Timer TimerValue Register (EL2) Counter-timer Hypervisor Physical Timer Control Register Counter-timer Physical Timer CompareValue Register (EL2) Counter-timer Physical Timer TimerValue Register (EL2) Counter-timer Secure Virtual Timer Control Register (EL2) Counter-timer Secure Virtual Timer CompareValue Register (EL2) Counter-timer Secure Virtual Timer TimerValue Register (EL2) Counter-timer Virtual Timer Control Register (EL2) Counter-timer Virtual Timer CompareValue Register (EL2) Counter-timer Virtual Timer TimerValue Register (EL2) Counter-timer Kernel Control Register Counter-timer Self-Synchronized Physical Count Register Counter-timer Physical Count Register Counter-timer Physical Offset Register Counter-timer Physical Secure Timer Control Register Counter-timer Physical Secure Timer CompareValue Register Counter-timer Physical Secure Timer TimerValue Register Counter-timer Physical Timer Control Register Counter-timer Physical Timer CompareValue Register Counter-timer Physical Timer TimerValue Register Counter-timer Self-Synchronized Virtual Count Register Counter-timer Virtual Count Register Counter-timer Virtual Offset Register Counter-timer Virtual Timer Control Register Counter-timer Virtual Timer CompareValue Register Counter-timer Virtual Timer TimerValue Register Context ID Register (EL1) Context ID Register (EL2) Architectural Feature Access Control Masking Register Architectural Feature Access Control Register Architectural Feature Trap Masking Register Architectural Feature Trap Register (EL2) Architectural Feature Trap Register (EL3) Cache Size Selection Register Cache Type Register Current Exception Level Domain Access Control Register Interrupt Mask Bits Debug Authentication Status Register Debug Breakpoint Control Registers Debug Breakpoint Value Registers Debug CLAIM Tag Clear Register Debug CLAIM Tag Set Register Debug Data Transfer Register, Receive Debug Data Transfer Register, Transmit Debug Data Transfer Register, half-duplex Debug Power Control Register Debug Vector Catch Register Debug Watchpoint Control Registers Debug Watchpoint Value Registers Data Cache Zero ID Register Deferred Interrupt Status Register Data Independent Timing Debug Link Register Debug Saved Program Status Register Exception Link Register (EL1) Exception Link Register (EL2) Exception Link Register (EL3) Error Record ID Register Error Record Select Register Selected Error Record Address Register Selected Error Record Control Register Selected Error Record Feature Register Selected Error Record Group Status Register Selected Error Record Miscellaneous Register 0 Selected Error Record Miscellaneous Register 1 Selected Error Record Miscellaneous Register 2 Selected Error Record Miscellaneous Register 3 Selected Pseudo-fault Generation Countdown Register Selected Pseudo-fault Generation Control Register Selected Pseudo-fault Generation Feature Register Selected Error Record Primary Status Register Exception Syndrome Register (EL1) Exception Syndrome Register (EL2) Exception Syndrome Register (EL3) Fault Address Register (EL1) Fault Address Register (EL2) Fault Address Register (EL3) Fine-Grained Write Traps EL3 Floating-point Control Register Floating-Point Exception Control Register Floating-point Mode Register Floating-point Status Register Tag Control Register. Guarded Control Stack Control Register (EL0) Guarded Control Stack Control Register (EL1) Guarded Control Stack Control Register (EL2) Guarded Control Stack Control Register (EL3) Guarded Control Stack Pointer Register (EL0) Guarded Control Stack Pointer Register (EL1) Guarded Control Stack Pointer Register (EL2) Guarded Control Stack Pointer Register (EL3) Multiple tag transfer ID Register Granule Protection Check Bypass Window Register (EL3) Granule Protection Check Control Register (EL3) Granule Protection Table Base Register Hardware Accelerator for Cleaning Dirty State Base Register Hardware Accelerator for Cleaning Dirty State Consumer Register Hypervisor Auxiliary Control Register Hypervisor Activity Monitors Fine-Grained Read Trap Register Extended Hypervisor Configuration Register Hypervisor Configuration Register Hardware Dirty State Tracking Structure Base Register Hardware Dirty State Tracking Structure Producer Register Hypervisor Debug Fine-Grained Read Trap Register 2 Hypervisor Debug Fine-Grained Read Trap Register Hypervisor Debug Fine-Grained Write Trap Register 2 Hypervisor Debug Fine-Grained Write Trap Register Hypervisor Fine-Grained Instruction Trap Register 2 Hypervisor Fine-Grained Instruction Trap Register Hypervisor Fine-Grained Read Trap Register 2 Hypervisor Fine-Grained Read Trap Register Hypervisor Fine-Grained Write Trap Register 2 Hypervisor Fine-Grained Write Trap Register Hypervisor IPA Fault Address Register Hypervisor System Trap Register Interrupt Controller Active Priorities Group 0 Registers Interrupt Controller Active Priorities Group 1 Registers Interrupt Controller Alias Software Generated Interrupt Group 1 Register Interrupt Controller Binary Point Register 0 Interrupt Controller Binary Point Register 1 Interrupt Controller Control Register (EL1) Interrupt Controller Control Register (EL3) Interrupt Controller Deactivate Interrupt Register Interrupt Controller End Of Interrupt Register 0 Interrupt Controller End Of Interrupt Register 1 Interrupt Controller Highest Priority Pending Interrupt Register 0 Interrupt Controller Highest Priority Pending Interrupt Register 1 Interrupt Controller Interrupt Acknowledge Register 0 Interrupt Controller Interrupt Acknowledge Register 1 Interrupt Controller Interrupt Group 0 Enable Register Interrupt Controller Interrupt Group 1 Enable Register Interrupt Controller Interrupt Group 1 Enable Register (EL3) Interrupt Controller Non-maskable Interrupt Acknowledge Register 1 Interrupt Controller Interrupt Priority Mask Register Interrupt Controller Running Priority Register Interrupt Controller Software Generated Interrupt Group 0 Register Interrupt Controller Software Generated Interrupt Group 1 Register Interrupt Controller System Register Enable Register (EL1) Interrupt Controller System Register Enable Register (EL2) Interrupt Controller System Register Enable Register (EL3) Interrupt Controller Hyp Active Priorities Group 0 Registers Interrupt Controller Hyp Active Priorities Group 1 Registers Interrupt Controller End of Interrupt Status Register Interrupt Controller Empty List Register Status Register Interrupt Controller Hyp Control Register Interrupt Controller List Registers Interrupt Controller Maintenance Interrupt State Register Interrupt Controller Virtual Machine Control Register Interrupt Controller VGIC Type Register Interrupt Controller Virtual Active Priorities Group 0 Registers Interrupt Controller Virtual Active Priorities Group 1 Registers Interrupt Controller Virtual Binary Point Register 0 Interrupt Controller Virtual Binary Point Register 1 Interrupt Controller Virtual Control Register Interrupt Controller Deactivate Virtual Interrupt Register Interrupt Controller Virtual End Of Interrupt Register 0 Interrupt Controller Virtual End Of Interrupt Register 1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1 Interrupt Controller Virtual Interrupt Acknowledge Register 0 Interrupt Controller Virtual Interrupt Acknowledge Register 1 Interrupt Controller Virtual Interrupt Group 0 Enable Register Interrupt Controller Virtual Interrupt Group 1 Enable Register Interrupt Controller Virtual Non-maskable Interrupt Acknowledge Register 1 Interrupt Controller Virtual Interrupt Priority Mask Register Interrupt Controller Virtual Running Priority Register AArch64 Auxiliary Feature Register 0 AArch64 Auxiliary Feature Register 1 AArch64 Debug Feature Register 0 AArch64 Debug Feature Register 1 AArch64 Debug Feature Register 2 AArch64 Floating-point Feature Register 0 AArch64 Instruction Set Attribute Register 0 AArch64 Instruction Set Attribute Register 1 AArch64 Instruction Set Attribute Register 2 AArch64 Instruction Set Attribute Register 3 AArch64 Memory Model Feature Register 0 AArch64 Memory Model Feature Register 1 AArch64 Memory Model Feature Register 2 AArch64 Memory Model Feature Register 3 AArch64 Memory Model Feature Register 4 AArch64 Processor Feature Register 0 AArch64 Processor Feature Register 1 AArch64 Processor Feature Register 2 SME Feature ID Register 0 SVE Feature ID Register 0 AArch32 Auxiliary Feature Register 0 AArch32 Debug Feature Register 0 AArch32 Debug Feature Register 1 AArch32 Instruction Set Attribute Register 0 AArch32 Instruction Set Attribute Register 1 AArch32 Instruction Set Attribute Register 2 AArch32 Instruction Set Attribute Register 3 AArch32 Instruction Set Attribute Register 4 AArch32 Instruction Set Attribute Register 5 AArch32 Instruction Set Attribute Register 6 AArch32 Memory Model Feature Register 0 AArch32 Memory Model Feature Register 1 AArch32 Memory Model Feature Register 2 AArch32 Memory Model Feature Register 3 AArch32 Memory Model Feature Register 4 AArch32 Memory Model Feature Register 5 AArch32 Processor Feature Register 0 AArch32 Processor Feature Register 1 AArch32 Processor Feature Register 2 Instruction Fault Status Register (EL2) Interrupt Status Register LORegion Control (EL1) LORegion End Address (EL1) LORegionID (EL1) LORegion Number (EL1) LORegion Start Address (EL1) Extended Memory Attribute Indirection Register (EL1) Extended Memory Attribute Indirection Register (EL2) Extended Memory Attribute Indirection Register (EL3) Memory Attribute Indirection Register (EL1) Memory Attribute Indirection Register (EL2) Memory Attribute Indirection Register (EL3) Monitor DCC Interrupt Enable Register Monitor DCC Status Register Monitor Debug Configuration Register (EL2) Monitor Debug Configuration Register (EL3) Monitor Debug ROM Address Register Monitor Debug System Control Register Breakpoint and Watchpoint Selection Register Monitor Debug Step Opcode Register MEC Identification Register Alternate MECID for EL2 and EL2&0 translation regimes Alternate MECID for EL2&0 translation regimes. Primary MECID for EL2 and EL2&0 translation regimes Primary MECID for EL2&0 translation regimes Realm PA space Alternate MECID for EL3 stage 1 translation regime Physical Fault Address Register (EL3) Main ID Register MPAM0 Register (EL1) MPAM1 Register (EL1) MPAM2 Register (EL2) MPAM3 Register (EL3) MPAM PE-side Maximum Bandwidth Control Register (EL0) MPAM PE-side Maximum Bandwidth Control Register (EL1) MPAM PE-side Maximum Bandwidth Control Register (EL2) MPAM PE-side Maximum Bandwidth Control Register (EL3) MPAM PE-side Maximum Bandwidth Limit Virtualization Register MPAM PE-side Bandwidth Controls ID Register MPAM Streaming Mode Bandwidth Control Register (EL1) MPAM Hypervisor Control Register (EL2) MPAM ID Register (EL1) MPAM Streaming Mode Register MPAM Virtual PARTID Mapping Register 0 MPAM Virtual PARTID Mapping Register 1 MPAM Virtual PARTID Mapping Register 2 MPAM Virtual PARTID Mapping Register 3 MPAM Virtual PARTID Mapping Register 4 MPAM Virtual PARTID Mapping Register 5 MPAM Virtual PARTID Mapping Register 6 MPAM Virtual PARTID Mapping Register 7 MPAM Virtual Partition Mapping Valid Register Multiprocessor Affinity Register AArch32 Media and VFP Feature Register 0 AArch32 Media and VFP Feature Register 1 AArch32 Media and VFP Feature Register 2 Condition Flags OS Double Lock Register OS Lock Data Transfer Register, Receive OS Lock Data Transfer Register, Transmit OS Lock Exception Catch Control Register OS Lock Access Register OS Lock Status Register Privileged Access Never Physical Address Register Physical Fault Address Register (EL1) Physical Fault Address Register (EL2) Permission Indirection Register 0 (EL1) Permission Indirection Register 0 (EL2) Permission Indirection Register 1 (EL1) Permission Indirection Register 2 (EL2) Permission Indirection Register 3 (EL3) Profiling Exception Mask Profiling Buffer ID Register Profiling Buffer Limit Address Register Profiling Buffer Memory Attribute Register Profiling Buffer Write Pointer Register Profiling Buffer Status/syndrome Register (EL1) Profiling Buffer Syndrome Register (EL2) Profiling Buffer Syndrome Register (EL3) Performance Monitors Cycle Count Filter Register Performance Monitors Cycle Count Register Performance Monitors Cycle Count Saved Value Register Performance Monitors Common Event Identification Register 0 Performance Monitors Common Event Identification Register 1 Performance Monitors Count Enable Clear Register Performance Monitors Count Enable Set Register Performance Monitors Control Register Performance Monitors Extended Control Register (EL1) Performance Monitors Event Count Registers Performance Monitors Event Count Saved Value Registers Performance Monitors Event Type Registers Performance Monitors Instruction Counter Filter Register Performance Monitors Instruction Counter Register Performance Monitors Instruction Count Saved Value Register Performance Monitors Interrupt Enable Clear Register Performance Monitors Interrupt Enable Set Register Performance Monitors Machine Identification Register Performance Monitors Overflow Flag Status Clear Register Performance Monitors Overflow Flag Status Set Register Statistical Profiling Control Register (EL1) Statistical Profiling Control Register (EL2) Sampling Data Source Filter Register Performance Monitors Event Counter Selection Register Sampling Event Filter Register Sampling Filter Control Register Sampling Interval Counter Register Sampling Profiling ID Register Sampling Interval Reload Register Sampling Latency Filter Register Sampling Inverted Event Filter Register Performance Monitors Snapshot Status and Capture Register Performance Monitors Software Increment Register Performance Monitors User Access Control Register Performance Monitors User Enable Register Performance Monitors Selected Event Count Register Performance Monitors Selected Event Type Register Performance Monitors Zero with Mask Permission Overlay Register 0 (EL0) Permission Overlay Register 1 (EL1) Permission Overlay Register 2 (EL2) Permission Overlay Register 3 (EL3) Read Check Write Instruction Mask (EL1) Software Read Check Write Instruction Mask (EL1) Revision ID Register Random Allocation Tag Seed Register. Reset Management Register (EL1) Reset Management Register (EL2) Reset Management Register (EL3) Random Number Random Number Full Entropy Reset Vector Base Address Register (if EL2 and EL3 not implemented) Reset Vector Base Address Register (if EL3 not implemented) Reset Vector Base Address Register (if EL3 implemented) Stage 2 Permission Indirection Register (EL2) Stage 2 Permission Overlay Register (EL1) IMPLEMENTATION DEFINED Registers Secure Configuration Register Extended System Control Masking Register (EL1) Extended System Control Masking Register (EL2) System Control Register (EL1) System Control Register (EL2) System Control Register (EL3) System Control Masking Register (EL1) System Control Masking Register (EL2) System Control Register (EL1) System Control Register (EL2) System Control Register (EL3) EL0 Read/Write Software Context Number EL1 Read/Write Software Context Number EL2 Read/Write Software Context Number EL3 Read/Write Software Context Number AArch32 Secure Debug Enable Register AArch32 Secure Debug Enable Register SME Control Register (EL1) SME Control Register (EL2) SME Control Register (EL3) Streaming Mode Identification Register Streaming Mode Priority Mapping Register Streaming Mode Priority Register System Performance Monitors Access Register (EL1) System Performance Monitors Access Register (EL2) System Performance Monitors Access Register (EL3) System Performance Monitors Configuration Register System PMU Counter Group Configuration Registers System Performance Monitors Count Enable Clear Register System Performance Monitors Count Enable Set Register System Performance Monitor Control Register System Performance Monitors Device Affinity Register System Performance Monitors Device Architecture Register System Performance Monitors Event Count Register System Performance Monitors Event Filter Control Register 2 System Performance Monitors Event Filter Control Register System Performance Monitors Event Type Register System PMU Implementation Identification Register System Performance Monitors Interrupt Enable Clear Register System Performance Monitors Interrupt Enable Set Register System Performance Monitors Overflow Flag Status Clear Register System Performance Monitors Overflow Flag Status Set Register System Performance Monitors Root and Realm Control Register System Performance Monitors Secure Control Register System Performance Monitors Select Register System Performance Monitors Zero with Mask Saved Program Status Register (EL1) Saved Program Status Register (EL2) Saved Program Status Register (EL3) Saved Program Status Register (Abort mode) Saved Program Status Register (FIQ mode) Saved Program Status Register (IRQ mode) Saved Program Status Register (Undefined mode) Stack Pointer Select Stack Pointer (EL0) Stack Pointer (EL1) Stack Pointer (EL2) Stack Pointer (EL3) Speculative Store Bypass Safe Streaming Vector Control Register Tag Check Override Extended Translation Control Masking Register (EL1) Extended Translation Control Masking Register (EL2) Extended Translation Control Register (EL1) Extended Translation Control Register (EL2) Translation Control Masking Register (EL1) Translation Control Masking Register (EL2) Translation Control Register (EL1) Translation Control Register (EL2) Translation Control Register (EL3) Tag Fault Status Register (EL0). Tag Fault Status Register (EL1) Tag Fault Status Register (EL2) Tag Fault Status Register (EL3) EL0 Read/Write Software Thread ID Register 2 EL0 Read-Only Software Thread ID Register EL0 Read/Write Software Thread ID Register EL1 Software Thread ID Register EL2 Software Thread ID Register EL3 Software Thread ID Register Trace Buffer Base Address Register Trace Buffer ID Register Trace Buffer Limit Address Register Trace Buffer Memory Attribute Register Trace Buffer MPAM Configuration Register Trace Buffer Write Pointer Register Trace Buffer Status/syndrome Register (EL1) Trace Buffer Syndrome Register (EL2) Trace Buffer Syndrome Register (EL3) Trace Buffer Trigger Counter Register Trace Address Comparator Access Type Register <n> Trace Address Comparator Value Register <n> Trace Authentication Status Register Trace Auxiliary Control Register Trace Branch Broadcast Control Register Trace Cycle Count Control Register Trace Context Identifier Comparator Control Register 0 Trace Context Identifier Comparator Control Register 1 Trace Context Identifier Comparator Value Registers <n> Trace Claim Tag Clear Register Trace Claim Tag Set Register Trace Counter Control Register <n> Trace Counter Reload Value Register <n> Trace Counter Value Register <n> Trace Configuration Register Trace Device Architecture Register Trace Device Configuration Register Trace Event Control 0 Register Trace Event Control 1 Register Trace External Input Select Register <n> Trace ID Register 0 Trace ID Register 1 Trace ID Register 10 Trace ID Register 11 Trace ID Register 12 Trace ID Register 13 Trace ID Register 2 Trace ID Register 3 Trace ID Register 4 Trace ID Register 5 Trace ID Register 6 Trace ID Register 7 Trace ID Register 8 Trace ID Register 9 Trace IMP DEF Register 0 Trace IMP DEF Register <n> Instrumentation Trace Control Register (EL1) Instrumentation Trace Control Register (EL2) Instrumentation Trace Extension External Debug Control Register Trace OS Lock Status Register Trace Programming Control Register Trace Q Element Control Register Trace Resource Selection Control Register <n> Trace Resources Status Register Trace Sequencer State Transition Control Register <n> Trace Sequencer Reset Control Register Trace Sequencer State Register Trace Single-shot Comparator Control Register <n> Trace Single-shot Comparator Control Status Register <n> Trace Single-shot Processing Element Comparator Input Control Register <n> Trace Stall Control Register Trace Status Register Trace Synchronization Period Register Trace ID Register Trace Timestamp Control Register Trace ViewInst Main Control Register Trace ViewInst Include/Exclude Control Register Trace ViewInst Start/Stop PE Comparator Control Register Trace ViewInst Start/Stop Control Register Trace Virtual Context Identifier Comparator Control Register 0 Trace Virtual Context Identifier Comparator Control Register 1 Trace Virtual Context Identifier Comparator Value Register <n> Trace Filter Control Register (EL1) Trace Filter Control Register (EL2) Translation Table Base Register 0 (EL1) Translation Table Base Register 0 (EL2) Translation Table Base Register 0 (EL3) Translation Table Base Register 1 (EL1) Translation Table Base Register 1 (EL2) User Access Override Vector Base Address Register (EL1) Vector Base Address Register (EL2) Vector Base Address Register (EL3) Virtual Deferred Interrupt Status Register (EL2) Virtual Deferred Interrupt Status Register (EL3) Alternate MECID for EL1&0 stage 2 translation regime Primary MECID for EL1&0 stage 2 translation regime Virtualization Multiprocessor ID Register Virtual Nested Control Register Virtualization Processor ID Register Virtual SError Exception Syndrome Register (EL2) Virtual SError Exception Syndrome Register (EL3) Virtualization Secure Translation Control Register Virtualization Secure Translation Table Base Register Virtualization Translation Control Register Virtualization Translation Table Base Register SVE Control Register (EL1) SVE Control Register (EL2) SVE Control Register (EL3) 2026-03-26 20:27:25 2026-03_rel