RGSR_EL1 Random Allocation Tag Seed Register. when FEAT_MTE2 is implemented Random Allocation Tag Seed Register. Generic System Control When GCR_EL1.RRND is 1, updates to RGSR_EL1 are implementation-specific. Direct and indirect reads and writes to the register appear to occur in program order relative to other instructions, without the need for any explicit synchronization. RGSR_EL1 is a 64-bit register. When GCR_EL1.RRND == '0' 63 24 63:24 Reserved, RES0. SEED 23 8 23:8 Seed register used for generating values returned by RandomTag(). AU 7 4 7:4 Reserved, RES0. TAG 3 0 3:0 Tag generated by the most recent IRG instruction. AU 63 56 63:56 Reserved, RES0. SEED 55 8 55:8 IMPLEMENTATION DEFINED. Software is recommended to avoid writing SEED[15:0] with a value of zero, unless this has been generated by the PE in response to an earlier value with SEED being nonzero. AU 7 4 7:4 Reserved, RES0. TAG 3 0 3:0 IMPLEMENTATION DEFINED. AU When GCR_EL1.RRND == '0' MRS <Xt>, RGSR_EL1 if !IsFeatureImplemented(FEAT_MTE2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = RGSR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = RGSR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = RGSR_EL1(); end; MSR RGSR_EL1, <Xt> if !IsFeatureImplemented(FEAT_MTE2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && !(IsFeatureImplemented(FEAT_MTE2) && HCR_EL2().ATA == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else RGSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then Undefined(); elsif HaveEL(EL3) && !(IsFeatureImplemented(FEAT_MTE2) && SCR_EL3().ATA == '1') then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else RGSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then RGSR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel