RMR_EL1 Reset Management Register (EL1) when the highest implemented Exception level is EL1 and FEAT_AA64 is implemented RMR Architectural AArch32 31 0 31 0 31 0 31 0 when the highest implemented Exception level is EL1 When this register is implemented: A write to the register at EL1 can request a Warm reset. If EL1 can use all Execution states, this register specifies the Execution state that the PE boots into on a Warm reset. Reset Management When EL1 is the highest implemented Exception level: If EL1 can use all Execution states then this register must be implemented. If EL1 cannot use AArch32 then it is IMPLEMENTATION DEFINED whether the register is implemented. RMR_EL1 is a 64-bit register. 63 2 63:2 Reserved, RES0. RR 1 1 1 Reset Request. Setting this bit to 1 requests a Warm reset. '0' AA64 0 0 0 Determines which Execution state the PE boots into after a Warm reset: On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state. 0b0 AArch32. 0b1 AArch64. '1' When Implementation can reset into AArch32 state 0 0 0 Reserved, RAO/WI. Otherwise MRS <Xt>, RMR_EL1 if !(IsHighestEL(EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL1 && IsHighestEL(EL1) then X{64}(t) = RMR_EL1(); else Undefined(); end; MSR RMR_EL1, <Xt> if !(IsHighestEL(EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL1 && IsHighestEL(EL1) then RMR_EL1() = X{64}(t); else Undefined(); end; 2026-03-26 20:27:25 2026-03_rel