S2PIR_EL2 Stage 2 Permission Indirection Register (EL2) when FEAT_S2PIE is implemented and FEAT_AA64 is implemented Stage 2 Permission Indirection Register for EL1&0 translation regime. Memory If EL2 is not implemented, this register is RES0 from EL3. S2PIR_EL2 is a 64-bit register. Perm<m> 63 0 63:0 Represents stage 2 Base Permissions. This field is permitted to be cached in a TLB. When stage 2 Indirect Permission mechanism is disabled, the contents of this register are ignored. 15 0 0b0000 No Access. 0b0001 Reserved - treated as No Access. 0b0010 MRO. 0b0011 MRO-TL1. 0b0100 WO. 0b0101 Reserved - treated as No Access. 0b0110 MRO-TL0. 0b0111 MRO-TL01. 0b1000 RO. 0b1001 RO+uX. 0b1010 RO+pX. 0b1011 RO+puX. 0b1100 RW. 0b1101 RW+uX. 0b1110 RW+pX. 0b1111 RW+puX. AU MRS <Xt>, S2PIR_EL2 if !(IsFeatureImplemented(FEAT_S2PIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x2B0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = S2PIR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = S2PIR_EL2(); end; MSR S2PIR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_S2PIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x2B0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().PIEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().PIEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else S2PIR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then S2PIR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel