SCR_EL3
Secure Configuration Register
when EL3 is implemented and FEAT_AA64 is implemented
Defines the configuration of the current Security state. It specifies:
The Security state of EL0, EL1, and EL2. The Security state is Secure, Non-secure, or Realm.
The Execution state at lower Exception levels.
Whether IRQ, FIQ, SError exceptions, and External abort exceptions are taken to EL3.
Whether various operations are trapped to EL3.
Secure
SCR_EL3 is a 64-bit register.
63
63
63
Reserved, RES0.
NSE
62
62
0
This field, evaluated with SCR_EL3.NS, selects the Security state of EL2 and lower Exception levels.
For a description of the values derived by evaluating NS and NSE together, see SCR_EL3.NS.
AU
When FEAT_RME is implemented
NSE
62
62
0
The Effective value of this bit is 0.
RES0
Otherwise
HACDBSEn
61
61
0
Enables access to the HACDBSBR_EL2 and HACDBSCONS_EL2 registers at EL2.
Traps are reported using EC syndrome value 0x18.
0b0
EL2 accesses to the specified registers are trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_HACDBS is implemented
61
61
61
Reserved, RES0.
Otherwise
HDBSSEn
60
60
0
Enables access to HDBSSBR_EL2 and HDBSSPROD_EL2 registers at EL2.
Traps are reported using EC syndrome value 0x18.
0b0
EL2 accesses to the specified registers are trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_HDBSS is implemented
60
60
60
Reserved, RES0.
Otherwise
FGTEn2
59
59
0
Fine-Grained Traps Enable 2.
When EL2 is implemented, enables the traps to EL2 controlled by HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2, HFGRTR2_EL2, and HFGWTR2_EL2, and controls access to those registers.
Traps caused by accesses to the fine-grained trap registers are reported using EC syndrome value 0x18 and its associated ISS.
0b0
EL2 accesses to the specified registers are trapped to EL3. The values in these registers are treated as 0.
0b1
EL2 accesses to the specified registers are not trapped to EL3 by this mechanism.
AU
When FEAT_FGT2 is implemented
59
59
59
Reserved, RES0.
Otherwise
EnDSE
58
58
0
Enable for delegated SError exceptions pended by SCR_EL3.DSE.
This field is ignored by the PE and treated as zero if SCR_EL3.EA is 0 and the Effective value of SCR_EL3.TMEA is 0.
0b0
Delegated SError exceptions pended by SCR_EL3.DSE are disabled.
0b1
Delegated SError exceptions pended by SCR_EL3.DSE are enabled.
AU
When FEAT_E3DSE is implemented
58
58
58
Reserved, RES0.
Otherwise
DSE
57
57
0
Delegated SError exception for EL2, EL1, and EL0.
When EL2 is implemented and enabled in the current Security state, delegated SError exceptions pended by this field are affected by HCR_EL2.AMO and HCRX_EL2.TMEA.
Virtual SError exceptions pended by HCR_EL2.VSE have priority over delegated SError exceptions pended by this field.
This field is ignored by the PE and treated as zero when SCR_EL3.EnDSE == 0
0b0
This mechanism is not making a delegated SError exception pending.
0b1
A delegated SError exception for EL2, EL1, and EL0 is pending because of this mechanism.
AU
When FEAT_E3DSE is implemented
57
57
57
Reserved, RES0.
Otherwise
56
56
56
Reserved, RES0.
EnIDCP128
55
55
0
Enables access to IMPLEMENTATION DEFINED 128-bit System registers.
0b0
Accesses at EL2, EL1, EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL3 using EC syndrome value 0x14, unless the access generates a higher priority exception.
Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL3.
0b1
No accesses are trapped by this control.
AU
When FEAT_SYSREG128 is implemented
55
55
55
Reserved, RES0.
Otherwise
SRMASKEn
54
54
0
Enables access to the following MASK registers:
CPACRMASK_EL1, and CPACRMASK_EL12.
SCTLRMASK_EL1, and SCTLRMASK_EL12.
SCTLR2MASK_EL1, and SCTLR2MASK_EL12.
TCRMASK_EL1, and TCRMASK_EL12.
TCR2MASK_EL1, and TCR2MASK_EL12.
ACTLRMASK_EL1 and ACTLRMASK_EL12, if they are implemented.
CPTRMASK_EL2.
SCTLRMASK_EL2.
SCTLR2MASK_EL2.
TCRMASK_EL2.
TCR2MASK_EL2.
ACTLRMASK_EL2, if it is implemented.
Traps are reported using EC syndrome value 0x18.
Traps generated by this control have a lower priority than traps generated by the HCRX_EL2.SRMASKEn, HFGRTR2_EL2 and HFGWTR2_EL2 controls.
0b0
EL2 accesses to the specified registers are trapped to EL3. EL1 accesses to the specified EL1 registers are trapped to EL3.
The values in the registers are treated as 0.
0b1
No accesses are trapped by this control.
AU
When FEAT_SRMASK is implemented
54
54
54
Reserved, RES0.
Otherwise
PFAREn
53
53
0
Enable access to Physical Fault Address Registers. When disabled, accesses to Physical Fault Address Registers generate a trap to EL3.
In AArch64 state, the instructions affected by this control are: MRS and MSR accesses to PFAR_EL1, PFAR_EL2, and PFAR_EL12.
Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.
Trapped instructions are reported using EC syndrome value 0x18.
0b0
Accesses of the specified Physical Fault Address Registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_PFAR is implemented
53
53
53
Reserved, RES0.
Otherwise
TWERR
52
52
0
Trap writes of Error Record registers. Enables a trap to EL3 on writes of Error Record registers.
In AArch64 state, the instructions affected by this control are: MSR accesses to ERRSELR_EL1, ERXADDR_EL1, ERXCTLR_EL1, ERXMISC0_EL1, ERXMISC1_EL1, ERXMISC2_EL1, ERXMISC3_EL1, and ERXSTATUS_EL1.
In AArch32 state, the instructions affected by this control are: MCR accesses to ERRSELR, ERXADDR, ERXADDR2, ERXCTLR, ERXCTLR2, ERXMISC0, ERXMISC1, ERXMISC2, ERXMISC3, ERXMISC4, ERXMISC5, ERXMISC6, ERXMISC7, and ERXSTATUS.
Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.
Trapped AArch64 instructions are reported using EC syndrome value 0x18.
Trapped AArch32 instructions are reported using EC syndrome value 0x03.
Accessing this field has the following behavior:
This field is permitted to be RES0 if all of the following are true:
ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI.
ERRIDR_EL1.NUM is zero.
0b0
This control does not cause any instructions to be trapped.
0b1
Writes of the specified Error Record registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.
AU
When FEAT_RASv2 is implemented
52
52
52
Reserved, RES0.
Otherwise
TMEA
51
51
0
Trap Masked External Aborts. Controls whether a masked error exception at a lower Exception level is taken to EL3.
This field has no effect on the routing of virtual or delegated SError exceptions.
0b0
Synchronous External abort exceptions and SError exceptions at EL2, EL1, and EL0 are unaffected by this mechanism. That is, these exceptions are not taken to EL3 unless routed to EL3 by another control.
0b1
When executing at Exception levels below EL3, all of the following apply:
When PSTATE.A is 1, synchronous External abort exceptions are taken to EL3, unless they are taken from EL1 or EL0 and routed to EL2 by another control.
Masked physical SError exceptions are taken to EL3, unless they are taken from EL1 or EL0 and routed to EL2 by another control.
AU
When FEAT_DoubleFault2 is implemented
51
51
51
Reserved, RES0.
Otherwise
EnFPM
50
50
0
Enables direct and indirect accesses to FPMR from EL2, EL1, and EL0.
When accesses to FPMR are disabled by this control:
Direct accesses to FPMR from EL2, EL1, and EL0 are trapped to EL3 and reported with EC syndrome value 0x18.
Execution of FP8 data-processing instructions that indirectly access FPMR is UNDEFINED at EL2, EL1 and EL0.
Traps are not taken if there is a higher priority exception generated by the access.
If EL3 is not implemented, the Effective value of this field is 1.
0b0
Direct and indirect accesses to FPMR are disabled at EL2, EL1 and EL0.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_FPMR is implemented
50
50
50
Reserved, RES0.
Otherwise
MECEn
49
49
0
Enables access to the following EL2 MECID registers, from EL2:
MECID_P0_EL2.
MECID_A0_EL2
MECID_P1_EL2
MECID_A1_EL2
VMECID_P_EL2
VMECID_A_EL2
Accesses to these registers are trapped and reported using EC syndrome value 0x18.
0b0
EL2 accesses to any of the specified registers are trapped to EL3. The values of the specified registers are treated as 0 for all purposes other than direct reads or writes to the register from EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_MEC is implemented
49
49
49
Reserved, RES0.
Otherwise
GPF
48
48
0
Controls the reporting of Granule protection faults at EL0, EL1 and EL2.
0b0
This control does not cause exceptions to be routed from EL0, EL1 or EL2 to EL3.
0b1
GPFs at EL0, EL1 and EL2 are routed to EL3 and reported as Granule Protection Check exceptions.
AU
When FEAT_RME is implemented
48
48
48
Reserved, RES0.
Otherwise
D128En
47
47
0
128-bit System Register trap control. Enables access to 128-bit System Registers via MRRS, MSRR instructions.
MRRS and MSRR accesses from EL1 and EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x14:
TTBR0_EL1.
TTBR1_EL1.
RCWMASK_EL1, RCWSMASK_EL1.
PAR_EL1.
MRRS and MSRR accesses from EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x14:
TTBR1_EL2 and accesses using the register name TTBR1_EL12.
TTBR0_EL2 and accesses using the register name TTBR0_EL12.
VTTBR_EL2.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
EL1 and EL2 accesses to the specified registers are disabled, and trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_D128 is implemented
47
47
47
Reserved, RES0.
Otherwise
AIEn
46
46
0
MAIR2_ELx, AMAIR2_ELx Register access trap control.
Accesses from EL1 and EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x18:
AMAIR2_EL1.
MAIR2_EL1.
Accesses from EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x18:
AMAIR2_EL2 and accesses using the register name AMAIR2_EL12.
MAIR2_EL2 and accesses using the register name MAIR2_EL12.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
EL1 and EL2 accesses to the specified registers are disabled, and trapped to EL3. The values in these registers are treated as 0.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_AIE is implemented
46
46
46
Reserved, RES0.
Otherwise
PIEn
45
45
0
Permission Indirection, Overlay Register access trap control. Enables access to Permission Indirection and Overlay registers.
Accesses from EL0, EL1 and EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x18:
POR_EL0.
Accesses from EL1 and EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x18:
PIRE0_EL1.
PIR_EL1.
POR_EL1.
S2POR_EL1.
Accesses from EL2 using AArch64 to the following registers are trapped and reported using EC syndrome value 0x18:
PIRE0_EL2 and accesses using the register name PIRE0_EL12.
PIR_EL2 and accesses using the register name PIR_EL12.
POR_EL2 and accesses using the register name POR_EL12.
S2PIR_EL2.
If this field is 0, it is IMPLEMENTATION SPECIFIC whether the values of the named registers are treated as zero.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
EL0, EL1 and EL2 accesses to the specified registers are disabled, and trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_S1PIE is implemented, or FEAT_S2PIE is implemented, or FEAT_S1POE is implemented, or FEAT_S2POE is implemented
45
45
45
Reserved, RES0.
Otherwise
SCTLR2En
44
44
0
SCTLR2_ELx register trap control. Enables access to SCTLR2_EL1 and SCTLR2_EL2 registers.
Traps are reported using EC syndrome value 0x18.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
EL1 and EL2 accesses to SCTLR2_EL1 and SCTLR2_EL2 registers are disabled, and trapped to EL3. The values in these registers are treated as 0.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_SCTLR2 is implemented
44
44
44
Reserved, RES0.
Otherwise
TCR2En
43
43
0
TCR2_ELx register trap control. Enables access to TCR2_EL1 and TCR2_EL2 registers.
Traps are reported using EC syndrome value 0x18.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
EL1 and EL2 accesses to TCR2_EL1 and TCR2_EL2 registers are disabled, and trapped to EL3. The values in these registers are treated as 0.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_TCR2 is implemented
43
43
43
Reserved, RES0.
Otherwise
RCWMASKEn
42
42
0
RCW and RCWS Mask register trap control. Enables access to RCWMASK_EL1, RCWSMASK_EL1.
Traps for MRS, MSR access are reported using EC syndrome value 0x18.
Traps for MRRS, MSRR acceess are reported using EC syndrome value 0x14.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
EL1 and EL2 accesses to RCWMASK_EL1 and RCWSMASK_EL1 registers are disabled, and trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_THE is implemented
42
42
42
Reserved, RES0.
Otherwise
EnTP2
41
41
0
Traps instructions executed at EL2, EL1, and EL0 that access TPIDR2_EL0 to EL3. The exception is reported using EC syndrome value 0x18.
0b0
This control causes execution of these instructions at EL2, EL1, and EL0 to be trapped.
0b1
This control does not cause execution of any instructions to be trapped.
AU
When FEAT_SME is implemented
41
41
41
Reserved, RES0.
Otherwise
TRNDR
40
40
0
Controls trapping of reads of RNDR and RNDRRS. The exception is reported using EC syndrome value 0x18.
When FEAT_RNG is not implemented, Arm recommends that SCR_EL3.TRNDR is initialized before entering Exception levels below EL3 and not subsequently changed.
0b0
This control does not cause RNDR and RNDRRS to be trapped.
When FEAT_RNG is implemented:
ID_AA64ISAR0_EL1.RNDR returns the value 0b0001.
When FEAT_RNG is not implemented:
ID_AA64ISAR0_EL1.RNDR returns the value 0b0000.
MRS reads of RNDR and RNDRRS are UNDEFINED.
0b1
ID_AA64ISAR0_EL1.RNDR returns the value 0b0001.
Any attempt to read RNDR or RNDRRS is trapped to EL3.
'0'
When FEAT_RNG_TRAP is implemented
40
40
40
Reserved, RES0.
Otherwise
GCSEn
39
39
0
Guarded Control Stack enable. Controls access to the Guarded Control Stack registers from EL2, EL1, and EL0, and controls whether the Guarded Control Stack is enabled.
The Guarded Control Stack registers trapped by this mechanism are:
GCSCRE0_EL1.
GCSCR_EL1.
GCSCR_EL2.
GCSCR_EL12.
GCSPR_EL0.
GCSPR_EL1.
GCSPR_EL2.
GCSPR_EL12.
Traps are reported using EC syndrome value 0x18.
Traps are not taken if there is a higher priority exception generated by the access.
0b0
Trap read and write accesses to all Guarded Control Stack registers to EL3. All Guarded Control Stack behavior is disabled at EL2, EL1, and EL0.
0b1
This control does not cause any instructions to be trapped, and does not disable Guarded Control Stack behavior at EL2, EL1, or EL0.
AU
When FEAT_GCS is implemented
39
39
39
Reserved, RES0.
Otherwise
HXEn
38
38
0
Enables access to the HCRX_EL2 register at EL2 from EL3.
When EL3 is not implemented, the Effective value of this field is 1.
0b0
Accesses at EL2 to HCRX_EL2 are trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_HCX is implemented
38
38
38
Reserved, RES0.
Otherwise
ADEn
37
37
0
Enables access to the ACCDATA_EL1 register at EL1 and EL2.
If the HFGWTR_EL2.nACCDATA_EL1 or HFGRTR_EL2.nACCDATA_EL1 traps are enabled, they take priority over this trap.
0b0
Accesses to ACCDATA_EL1 at EL1 and EL2 are trapped to EL3, unless the accesses are trapped to EL2 by the EL2 fine-grained trap.
0b1
This control does not cause accesses to ACCDATA_EL1 to be trapped.
AU
When FEAT_LS64_ACCDATA is implemented
37
37
37
Reserved, RES0.
Otherwise
EnAS0
36
36
0
Traps execution of an ST64BV0 instruction at EL0, EL1, or EL2 to EL3.
A trap of an ST64BV0 instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000001.
0b0
EL0 execution of an ST64BV0 instruction is trapped to EL3, unless it is trapped to EL1 by SCTLR_EL1.EnAS0, or to EL2 by either HCRX_EL2.EnAS0 or SCTLR_EL2.EnAS0.
EL1 execution of an ST64BV0 instruction is trapped to EL3, unless it is trapped to EL2 by HCRX_EL2.EnAS0.
EL2 execution of an ST64BV0 instruction is trapped to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_LS64_ACCDATA is implemented
36
36
36
Reserved, RES0.
Otherwise
AMVOFFEN
35
35
0
Activity Monitors Virtual Offsets Enable.
0b0
Accesses to AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 at EL2 are trapped to EL3. Indirect reads of the virtual offset registers are zero.
0b1
Accesses to AMEVCNTVOFF0<n>_EL2 and AMEVCNTVOFF1<n>_EL2 are not affected by this field.
AU
When FEAT_AMUv1p1 is implemented
35
35
35
Reserved, RES0.
Otherwise
34
34
34
Reserved, RES0.
TWEDEL
33
30
3:0
TWE Delay. A 4-bit unsigned number that, when SCR_EL3.TWEDEn is 1, encodes the minimum delay in taking a trap of WFE* caused by SCR_EL3.TWE as 2(TWEDEL + 8) cycles.
AU
When FEAT_TWED is implemented
33
30
33:30
Reserved, RES0.
Otherwise
TWEDEn
29
29
0
TWE Delay Enable. Enables a configurable delayed trap of the WFE* instruction caused by SCR_EL3.TWE.
Traps are reported using EC syndrome value 0x01.
0b0
The delay for taking the trap is IMPLEMENTATION DEFINED.
0b1
The delay for taking the trap is at least the number of cycles defined in SCR_EL3.TWEDEL.
AU
When FEAT_TWED is implemented
29
29
29
Reserved, RES0.
Otherwise
ECVEn
28
28
0
ECV Enable. Enables access to the CNTPOFF_EL2 register.
When FEAT_ECV_POFF is not implemented, the Effective value of this field is 0.
0b0
EL2 accesses to CNTPOFF_EL2 are trapped to EL3, and the value of CNTPOFF_EL2 is treated as 0 for all purposes other than direct reads or writes to the register from EL3.
0b1
EL2 accesses to CNTPOFF_EL2 are not trapped to EL3 by this mechanism.
AU
When FEAT_ECV_POFF is implemented
28
28
28
Reserved, RES0.
Otherwise
FGTEn
27
27
0
Fine-Grained Traps Enable. When EL2 is implemented, enables the traps to EL2 controlled by HAFGRTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGRTR_EL2, HFGITR_EL2, and HFGWTR_EL2, and controls access to those registers.
If EL2 is not implemented but EL3 is implemented, FEAT_FGT implements the MDCR_EL3.TDCC traps.
Traps caused by accesses to the fine-grained trap registers are reported using EC syndrome value 0x18 and its associated ISS.
0b0
EL2 accesses to HAFGRTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGRTR_EL2, HFGITR_EL2 and HFGWTR_EL2 registers are trapped to EL3, and the traps to EL2 controlled by those registers are disabled.
0b1
EL2 accesses to HAFGRTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGRTR_EL2, HFGITR_EL2 and HFGWTR_EL2 registers are not trapped to EL3 by this mechanism.
AU
When FEAT_FGT is implemented
27
27
27
Reserved, RES0.
Otherwise
ATA
26
26
0
Memory tagging enable override:
Overrides enabling of Memory tagging at EL2, EL1 and EL0.
If disabled by this control and not trapped to EL2, accesses to the following registers at EL1 and EL2 are trapped to EL3 and reported using EC syndrome value 0x18:
GCR_EL1.
RGSR_EL1.
TFSRE0_EL1.
TFSR_EL1.
TFSR_EL2.
Accesses with the register name TFSR_EL12 that are not UNDEFINED.
When EL3 is not implemented, the Effective value of this field is 1.
0b0
Disables the use of Memory tagging at EL2, EL1 and EL0.
The specified registers are trapped to EL3 unless trapped to a lower Exception level.
0b1
This field does not disable the use of Memory tagging at EL2, EL1 and EL0.
The field does not trap the specified registers to EL3.
AU
When FEAT_MTE2 is implemented
26
26
26
Reserved, RES0.
Otherwise
EnSCXT
25
25
0
Enables access to the SCXTNUM_EL2, SCXTNUM_EL1, and SCXTNUM_EL0 registers.
0b0
Accesses at EL0, EL1 and EL2 to SCXTNUM_EL0, SCXTNUM_EL1, or SCXTNUM_EL2 registers are trapped to EL3 if they are not trapped by a higher priority exception, and the values of these registers are treated as 0.
0b1
This control does not cause any accesses to be trapped, or register values to be treated as 0.
AU
When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented
25
25
25
Reserved, RES0.
Otherwise
24
24
24
Reserved, RES0.
TID5
23
23
0
Trap ID group 5. EL2 and EL1 reads of the group 5 ID register GMID_EL1 are trapped to EL3, reported using EC syndrome value 0x18, unless the instruction generates a higher priority exception.
0b0
This control does not cause any instructions to be trapped.
0b1
The specified EL2 accesses to ID group 5 registers are trapped to EL3. When EL2 is not enabled in the current Security state, or when HCR_EL2.TID5 is 0, EL1 read accesses to the specified registers are trapped to EL3.
AU
When FEAT_IDTE3 is implemented and FEAT_MTE2 is implemented
23
23
23
Reserved, RES0.
Otherwise
TID3
22
22
0
Trap ID group 3. EL2 and EL1 reads of the following group 3 registers are trapped to EL3, reported using EC syndrome value 0x18, unless the instruction generates a higher priority exception:
ID_PFR0_EL1, ID_PFR1_EL1, ID_DFR0_EL1, ID_AFR0_EL1, ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, ID_ISAR5_EL1, MVFR0_EL1, MVFR1_EL1, and MVFR2_EL1.
ID_AA64PFR0_EL1, ID_AA64PFR1_EL1, ID_AA64DFR0_EL1, ID_AA64DFR1_EL1, ID_AA64ISAR0_EL1, ID_AA64ISAR1_EL1, ID_AA64MMFR0_EL1, ID_AA64MMFR1_EL1, ID_AA64AFR0_EL1, and ID_AA64AFR1_EL1.
ID_PFR2_EL1, and ID_MMFR4_EL1.
ID_MMFR5_EL1.
ID_AA64MMFR3_EL1.
ID_AA64MMFR4_EL1.
ID_AA64PFR2_EL1.
ID_AA64MMFR2_EL1 and ID_ISAR6_EL1.
ID_DFR1_EL1.
ID_AA64DFR2_EL1.
ID_AA64ZFR0_EL1.
ID_AA64SMFR0_EL1.
ID_AA64FPFR0_EL1.
ID_AA64ISAR2_EL1.
ID_AA64ISAR3_EL1.
This field traps all MRS accesses to registers in the following range that are not already mentioned in this field description: op0 == 3, op1 == 0, CRn == 0, CRm == {2-7}, op2 == {0-7}.
0b0
This control does not cause any instructions to be trapped.
0b1
The specified EL2 read accesses to ID group 3 registers are trapped to EL3. When EL2 is not enabled in the current Security state, or when HCR_EL2.TID3 is 0, EL1 read accesses to the specified registers are trapped to EL3.
AU
When FEAT_IDTE3 is implemented
22
22
22
Reserved, RES0.
Otherwise
FIEN
21
21
0
Fault Injection enable. Trap accesses to the registers ERXPFGCDN_EL1, ERXPFGCTL_EL1, and ERXPFGF_EL1 from EL1 and EL2 to EL3, reported using EC syndrome value 0x18.
If EL3 is not implemented, the Effective value of SCR_EL3.FIEN is 1.
If ERRIDR_EL1.NUM is zero, meaning no error records are implemented, or no error record accessible using System registers is owned by a node that implements the RAS Common Fault Injection Model Extension, then this bit might be RES0.
0b0
Accesses to the specified registers from EL1 and EL2 generate a Trap exception to EL3.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_RASv1p1 is implemented
21
21
21
Reserved, RES0.
Otherwise
NMEA
20
20
0
Non-maskable External Aborts. Controls whether PSTATE.A masks SError exceptions at EL3.
This field is ignored by the PE and treated as zero when all of the following are true:
FEAT_DoubleFault2 is not implemented.
SCR_EL3.EA is 0.
0b0
SError exceptions are not taken at EL3 if PSTATE.A == 1.
0b1
SError exceptions are taken at EL3 regardless of the value of PSTATE.A.
'0'
When FEAT_DoubleFault is implemented
20
20
20
Reserved, RES0.
Otherwise
EASE
19
19
0
External aborts to SError exception vector.
0b0
Synchronous External abort exceptions taken to EL3 are taken to the appropriate synchronous exception vector offset from VBAR_EL3.
0b1
Synchronous External abort exceptions taken to EL3 are taken to the appropriate SError exception vector offset from VBAR_EL3.
'0'
When FEAT_DoubleFault is implemented
19
19
19
Reserved, RES0.
Otherwise
EEL2
18
18
0
Secure EL2 Enable.
When the value of this bit is 1, then:
When SCR_EL3.NS == 0, the SCR_EL3.RW bit is treated as 1 for all purposes other than reading or writing the register.
If Secure EL1 is using AArch32, then any of the following operations, executed in Secure EL1, is trapped to Secure EL2, using EC syndrome value 0x03 :
A read or write of the SCR.
A read or write of the NSACR.
A read or write of the MVBAR.
A read or write of the SDCR.
Execution of an ATS12NSO** instruction.
If Secure EL1 is using AArch32, then any of the following operations, executed in Secure EL1, is trapped to Secure EL2 using EC syndrome value 0x00 :
Execution of an SRS instruction that uses R13_mon.
Execution of an MRS (Banked register) or MSR (Banked register) instruction that would access SPSR_mon, R13_mon, or R14_mon.
If the Effective value of SCR_EL3.EEL2 is 0, then these operations executed in Secure EL1 using AArch32 are trapped to EL3.A Secure only implementation that does not implement EL3 but implements EL2, behaves as if SCR_EL3.EEL2 == 1.
This bit is permitted to be cached in a TLB.
0b0
All behaviors associated with Secure EL2 are disabled. All registers, including timer registers, defined by FEAT_SEL2 are UNDEFINED, and those timers are disabled.
0b1
All behaviors associated with Secure EL2 are enabled.
AU
When FEAT_SEL2 is implemented
18
18
18
Reserved, RES0.
Otherwise
API
17
17
0
Controls the use of the following instructions related to Pointer Authentication.
PACGA.
AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZA, AUTIZB, PACDA, PACDB, PACDZA, PACDZB, PACIA, PACIA1716, PACIASP, PACIAZ, PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZA, PACIZB, RETAA, RETAB, BRAA, BRAB, BLRAA, BLRAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ, ERETAA, ERETAB, LDRAA and LDRAB, when any of the following are true:
In EL0, when the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and the associated SCTLR_EL1.En<N><M> == 1.
In EL0, when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, and the associated SCTLR_EL2.En<N><M> == 1.
In EL1, when the associated SCTLR_EL1.En<N><M> == 1.
In EL2, when the associated SCTLR_EL2.En<N><M> == 1.
When FEAT_PAuth_LR is implemented, AUTIASPPC, AUTIASPPCR, AUTIA171615, AUTIBSPPC, AUTIBSPPCR, AUTIB171615, PACIASPPC, PACNBIASPPC, PACIA171615, PACIBSPPC, PACNBIBSPPC, PACIB171615, RETAASPPC, RETAASPPCR, RETABSPPC, RETABSPPCR, when any of the following are true:
In EL0, when the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and the associated SCTLR_EL1.En<N><M> == 1.
In EL0, when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, and the associated SCTLR_EL2.En<N><M> == 1.
In EL1, when the associated SCTLR_EL1.En<N><M> == 1.
In EL2, when the associated SCTLR_EL2.En<N><M> == 1.
Traps are reported using EC syndrome value 0x09.
An instruction is trapped only if Pointer Authentication is enabled for that instruction, for more information, see 'PAC generation and verification keys'.
If FEAT_PAuth is implemented but EL3 is not implemented, the system behaves as if this bit is 1.
0b0
The specified instructions are trapped to EL3, when the instructions are enabled, unless they are trapped to EL2 as a result of the higher priority HCR_EL2.API trap.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_PAuth is implemented
17
17
17
Reserved, RES0.
Otherwise
APK
16
16
0
Trap registers holding "key" values for Pointer Authentication. Traps accesses to the following registers, using EC syndrome value 0x18, from EL1 or EL2 to EL3 unless they are trapped to EL2 as a result of the HCR_EL2.APK bit or other traps:
APIAKeyLo_EL1, APIAKeyHi_EL1, APIBKeyLo_EL1, APIBKeyHi_EL1.
APDAKeyLo_EL1, APDAKeyHi_EL1, APDBKeyLo_EL1, APDBKeyHi_EL1.
APGAKeyLo_EL1, and APGAKeyHi_EL1.
For more information, see 'PAC generation and verification keys'.
If FEAT_PAuth is implemented but EL3 is not implemented, the system behaves as if this bit is 1.
0b0
Access to the registers holding "key" values for pointer authentication from EL1 or EL2 are trapped to EL3 unless they are trapped to EL2 as a result of the HCR_EL2.APK bit or other traps.
0b1
This control does not cause any instructions to be trapped.
AU
When FEAT_PAuth is implemented
16
16
16
Reserved, RES0.
Otherwise
TERR
15
15
0
Trap accesses of Error Record registers. Enables a trap to EL3 on accesses of Error Record registers.
In AArch64 state, the instructions affected by this control are:
MRS and MSR accesses to ERRSELR_EL1, ERXADDR_EL1, ERXCTLR_EL1, ERXMISC0_EL1, ERXMISC1_EL1, and ERXSTATUS_EL1.
MRS accesses to ERRIDR_EL1 and ERXFR_EL1.
If FEAT_RASv1p1 is implemented, MRS and MSR accesses to ERXMISC2_EL1 and ERXMISC3_EL1.
If FEAT_RASv2 is implemented, MRS accesses to ERXGSR_EL1.
In AArch32 state, the instructions affected by this control are:
MRC and MCR accesses to ERRSELR, ERXADDR, ERXADDR2, ERXCTLR, ERXCTLR2, ERXMISC0, ERXMISC1, ERXMISC2, ERXMISC3, and ERXSTATUS.
MRC accesses to ERRIDR, ERXFR, and ERXFR2.
If FEAT_RASv1p1 is implemented, MRC and MCR accesses to ERXMISC4, ERXMISC5, ERXMISC6, and ERXMISC7.
Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.
Trapped AArch64 instructions are reported using EC syndrome value 0x18.
Trapped AArch32 instructions are reported using EC syndrome value 0x03.
Accessing this field has the following behavior:
This field is permitted to be RES0 if all of the following are true:
ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI.
ERRIDR_EL1.NUM is zero.
0b0
This control does not cause any instructions to be trapped.
0b1
Accesses of the specified Error Record registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.
AU
When FEAT_RAS is implemented
15
15
15
Reserved, RES0.
Otherwise
TLOR
14
14
0
Trap LOR registers. Traps Non-secure and Realm accesses to the LORSA_EL1, LOREA_EL1, LORN_EL1, LORC_EL1, and LORID_EL1 registers from EL1 and EL2 to EL3, unless the access has been trapped to EL2.
0b0
This control does not cause any instructions to be trapped.
0b1
Non-secure and Realm EL1 and EL2 accesses to the LOR registers that are not UNDEFINED are trapped to EL3, unless it is trapped by HCR_EL2.TLOR.
AU
When FEAT_LOR is implemented
14
14
14
Reserved, RES0.
Otherwise
TWE
13
13
13
Traps EL2, EL1, and EL0 execution of WFE instructions to EL3, from any Security state and both Execution states, reported using EC syndrome value 0x01.
When FEAT_WFxT is implemented, this trap also applies to the WFET instruction.
In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.For more information about when WFE instructions can cause the PE to enter a low-power state, see 'Wait for Event mechanism and Send event'.
0b0
This control does not cause any instructions to be trapped.
0b1
Any attempt to execute a WFE instruction at any Exception level lower than EL3 is trapped to EL3, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWE, HCR.TWE, SCTLR_EL1.nTWE, SCTLR_EL2.nTWE, or HCR_EL2.TWE.
AU
TWI
12
12
12
Traps EL2, EL1, and EL0 execution of WFI instructions to EL3, from any Security state and both Execution states, reported using EC syndrome value 0x01.
When FEAT_WFxT is implemented, this trap also applies to the WFIT instruction.
In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.For more information about when WFI instructions can cause the PE to enter a low-power state, see 'Wait for Interrupt'.
0b0
This control does not cause any instructions to be trapped.
0b1
Any attempt to execute a WFI instruction at any Exception level lower than EL3 is trapped to EL3, if the instruction would otherwise have caused the PE to enter a low-power state and it is not trapped by SCTLR.nTWI, HCR.TWI, SCTLR_EL1.nTWI, SCTLR_EL2.nTWI, or HCR_EL2.TWI.
AU
ST
11
11
11
Traps Secure EL1 accesses to the Counter-timer Physical Secure timer registers to EL3, from AArch64 state only, reported using EC syndrome value 0x18.
Accesses to the Counter-timer Physical Secure timer registers are always enabled at EL3. These registers are not accessible at EL0.
When FEAT_RME is implemented and Secure state is not implemented, this bit is RES0.
0b0
Secure EL1 using AArch64 accesses to the CNTPS_TVAL_EL1, CNTPS_CTL_EL1, and CNTPS_CVAL_EL1 are trapped to EL3 when Secure EL2 is disabled. If Secure EL2 is enabled, the behavior is as if the value of this field was 1.
0b1
This control does not cause any instructions to be trapped.
AU
RW
10
10
0
Execution state control for lower Exception levels.
If any of the following apply, then the Effective value of this bit is 1:
EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1.
The Effective value of SCR_EL3.{EEL2,NS} is {1,0}.
This bit is permitted to be cached in a TLB.
0b0
All lower Exception levels are using AArch32.
0b1
The next lower Exception level is using AArch64:
If EL2 is implemented and enabled in the Security state determined by SCR_EL3.{NSE,NS}, then EL2 is using AArch64 and EL2 controls the Execution state for EL1.
If EL2 is not implemented or EL2 is disabled in the Security state determined by SCR_EL3.{NSE,NS}, then EL1 is using AArch64.
When executing at EL0, if the next higher Exception level is using AArch64, then the Execution state is determined by PSTATE.nRW. Otherwise, EL0 uses AArch32.
AU
When FEAT_AA32EL1 is implemented
10
10
10
Reserved, RAO/WI.
Otherwise
SIF
9
9
9
Secure instruction fetch. When the PE is in Secure state, this bit disables instruction execution from memory marked in the first stage of translation as being Non-secure.
When FEAT_RME is implemented and Secure state is not implemented, this bit is RES0.
When FEAT_PAN3 is implemented, it is IMPLEMENTATION DEFINED whether SCR_EL3.SIF is also used to determine instruction access permission for the purpose of PAN.
This bit is permitted to be cached in a TLB.
0b0
Secure state instruction execution from memory marked in the first stage of translation as being Non-secure is permitted.
0b1
Secure state instruction execution from memory marked in the first stage of translation as being Non-secure is not permitted.
AU
HCE
8
8
8
Hypervisor Call instruction enable. Enables HVC instructions at EL3 and, if EL2 is enabled in the current Security state, at EL2 and EL1, in both Execution states, reported using EC syndrome value 0x00.
HVC instructions are always UNDEFINED at EL0 and, if Secure EL2 is disabled, at Secure EL1. Any resulting exception is taken from the current Exception level to the current Exception level.
If EL2 is not implemented, this bit is RES0.
0b0
HVC instructions are UNDEFINED.
0b1
HVC instructions are enabled at EL3, EL2, and EL1.
AU
SMD
7
7
7
Secure Monitor Call disable. Disables SMC instructions at EL1 and above, from any Security state and both Execution states, reported using EC syndrome value 0x00.
SMC instructions are always UNDEFINED at EL0. Any resulting exception is taken from the current Exception level to the current Exception level.
If HCR_EL2.TSC or HCR.TSC traps attempted EL1 execution of SMC instructions to EL2, that trap has priority over this disable.
0b0
SMC instructions are enabled at EL3, EL2 and EL1.
0b1
SMC instructions are UNDEFINED.
AU
6
6
6
Reserved, RES0.
5
4
5:4
Reserved, RES1.
EA
3
3
3
External Abort and SError exception routing.
This field has no effect on the routing of virtual or delegated SError exceptions.
For more information, see 'Asynchronous exception routing'.
0b0
When executing at Exception levels below EL3, External aborts and SError exceptions are not taken to EL3.
In addition, when executing at EL3:
SError exceptions are not taken.
External aborts are taken to EL3.
0b1
When executing at any Exception level, External aborts and SError exceptions are taken to EL3.
AU
FIQ
2
2
2
Physical FIQ Routing.
For more information, see 'Asynchronous exception routing'.
0b0
When executing at Exception levels below EL3, physical FIQ interrupts are not taken to EL3.
When executing at EL3, physical FIQ interrupts are not taken.
0b1
When executing at any Exception level, physical FIQ interrupts are taken to EL3.
AU
IRQ
1
1
1
Physical IRQ Routing.
For more information, see 'Asynchronous exception routing'.
0b0
When executing at Exception levels below EL3, physical IRQ interrupts are not taken to EL3.
When executing at EL3, physical IRQ interrupts are not taken.
0b1
When executing at any Exception level, physical IRQ interrupts are taken to EL3.
AU
NS
0
0
0
Non-secure bit. This field is used in combination with SCR_EL3.NSE to select the Security state of EL2 and lower Exception levels.
NSENSMeaning
0b00b0Secure.
0b00b1Non-secure.
0b10b0Reserved.
0b10b1Realm.
When Secure state is not implemented, SCR_EL3.NS is RES1 and its Effective value is 1.
AU
When FEAT_RME is implemented
NS
0
0
0
Non-secure bit.
0b0
Indicates that EL0 and EL1 are in Secure state.
When FEAT_SEL2 is implemented and SCR_EL3.EEL2 == 1, then EL2 is using AArch64 and in Secure state.
0b1
Indicates that Exception levels lower than EL3 are in Non-secure state, so memory accesses from those Exception levels cannot access Secure memory.
AU
Otherwise
MRS <Xt>, SCR_EL3
if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
X{64}(t) = SCR_EL3();
end;
MSR SCR_EL3, <Xt>
if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
SCR_EL3() = X{64}(t);
end;
2026-03-26 20:27:25
2026-03_rel