SCTLR2_EL2 System Control Register (EL2) when FEAT_SCTLR2 is implemented and FEAT_AA64 is implemented Provides top-level control of the system, including its memory system, at EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, these controls also apply to execution at EL0. Virt This register has no effect if EL2 is not enabled in the current Security state. SCTLR2_EL2 is a 64-bit register. 63 13 63:13 Reserved, RES0. CPTM0 12 12 0 This field controls unprivileged Checked Pointer Arithmetic for Multiplication. If HCR_EL2.TGE is 0, the field is IGNORED for all purposes other than direct reads and writes of the register. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. If the Effective value of SCTLR2_EL2.CPTA0 is 0, then the Effective value of this field is 0. 0b0 Pointer Arithmetic for Multiplication is not checked. 0b1 Pointer Arithmetic for Multiplication is checked. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.CPTM0 == '1' RO When FEAT_CPA2 is implemented and EffectiveHCR_EL2_E2H() == '1' 12 12 12 Reserved, RES0. Otherwise CPTM 11 11 0 This field controls Checked Pointer Arithmetic for Multiplication at EL2. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. If the Effective value of SCTLR2_EL2.CPTA is 0, then the Effective value of this field is 0. 0b0 Pointer Arithmetic for Multiplication is not checked. 0b1 Pointer Arithmetic for Multiplication is checked. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.CPTM == '1' RO When FEAT_CPA2 is implemented 11 11 11 Reserved, RES0. Otherwise CPTA0 10 10 0 This field controls unprivileged Checked Pointer Arithmetic for Addition. If HCR_EL2.TGE is 0, the field is IGNORED for all purposes other than direct reads and writes of the register. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 Pointer Arithmetic for Addition is not checked. 0b1 Pointer Arithmetic for Addition is checked. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.CPTA0 == '1' RO When FEAT_CPA2 is implemented and EffectiveHCR_EL2_E2H() == '1' 10 10 10 Reserved, RES0. Otherwise CPTA 9 9 0 This field controls Checked Pointer Arithmetic for Addition at EL2. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 Pointer Arithmetic for Addition is not checked. 0b1 Pointer Arithmetic for Addition is checked. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.CPTA == '1' RO When FEAT_CPA2 is implemented 9 9 9 Reserved, RES0. Otherwise EnPACM0 8 8 0 PACM Enable at EL0. Controls the effect of a PACM instruction at EL0. If HCR_EL2.TGE is 0, the field is IGNORED for all purposes other than direct reads and writes of the register. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 The effects of PACM are disabled at EL0. 0b1 A PACM instruction at EL0 causes PSTATE.PACM to be set to 1. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EnPACM0 == '1' RO When FEAT_PAuth_LR is implemented and EffectiveHCR_EL2_E2H() == '1' 8 8 8 Reserved, RES0. Otherwise EnPACM 7 7 0 PACM Enable at EL2. Controls the effect of a PACM instruction at EL2. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 The effects of PACM are disabled at EL2. 0b1 A PACM instruction at EL2 causes PSTATE.PACM to be set to 1. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EnPACM == '1' RO When FEAT_PAuth_LR is implemented 7 7 7 Reserved, RES0. Otherwise EnIDCP128 6 6 0 Enables access to IMPLEMENTATION DEFINED 128-bit System registers. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 Accesses at EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL2 using an ESR_EL2.EC value of 0x14, unless the access generates a higher priority exception. Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL2. 0b1 No accesses are trapped by this control. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EnIDCP128 == '1' RO When FEAT_SYSREG128 is implemented 6 6 6 Reserved, RES0. Otherwise EASE 5 5 0 External Aborts to SError exception vector. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 Synchronous External abort exceptions taken to EL2 are taken to the appropriate synchronous exception vector offset from VBAR_EL2. 0b1 Synchronous External abort exceptions taken to EL2 are taken to the appropriate SError exception vector offset from VBAR_EL2. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EASE == '1' RO When FEAT_DoubleFault2 is implemented 5 5 5 Reserved, RES0. Otherwise EnANERR 4 4 0 Enable Asynchronous Normal Read Error. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate. If FEAT_SVE is implemented, SCTLR2_EL2.EnANERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR. Setting this field to 0 might have a performance impact for Normal memory reads. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. Otherwise, this field is ignored by the PE and treated as one when all of the following are true: FEAT_ADERR is implemented. ID_AA64MMFR3_EL1.ANERR reads as 0b0010. SCTLR2_EL2.EnADERR is 1. 0b0 External aborts on Normal memory reads generate synchronous Data Abort exceptions in the EL2 and EL2&0 translation regimes. 0b1 External aborts on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL2 and EL2&0 translation regimes. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EnANERR == '1' RO When FEAT_ANERR is implemented 4 4 4 Reserved, RES0. Otherwise EnADERR 3 3 0 Enable Asynchronous Device Read Error. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate. If FEAT_SVE is implemented, SCTLR2_EL2.EnADERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR. Setting this field to 0 might have a performance impact for Device memory reads. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. Otherwise, this field is ignored by the PE and treated as one when all of the following are true: FEAT_ANERR is implemented. ID_AA64MMFR3_EL1.ADERR reads as 0b0010. SCTLR2_EL2.EnANERR is 1. 0b0 External aborts on Device memory reads generate synchronous Data Abort exceptions in the EL2 and EL2&0 translation regimes. 0b1 External aborts on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL2 and EL2&0 translation regimes. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EnADERR == '1' RO When FEAT_ADERR is implemented 3 3 3 Reserved, RES0. Otherwise NMEA 2 2 0 Non-maskable External Aborts. Controls whether physical SError exceptions are masked at EL2 when PSTATE.A is 1 or HCR_EL2.{AMO, TGE} is {0, 0}. This field has no effect on the masking of delegated SError interrupts. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. For more information, see 'Asynchronous exception routing'. 0b0 The masking of physical SError exceptions at EL2 is unaffected by this mechanism. 0b1 Physical SError exceptions are taken at EL2 regardless of whether they are masked by any mechanism, unless they are routed to EL3. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.NMEA == '1' RO When FEAT_DoubleFault2 is implemented 2 2 2 Reserved, RES0. Otherwise EMEC 1 1 0 Enables MEC. When enabled, memory accesses to the Realm physical address space are associated with a MECID. This bit is permitted to be cached in a TLB. When EL3 is implemented and SCR_EL3.SCTLR2En == 0, this field is ignored by the PE and treated as zero. 0b0 MEC is not enabled for the Realm physical address space. 0b1 MEC is enabled for the Realm physical address space. '0' AU FEAT_SRMASK is implemented EL2 is the current Exception level IsSystemRegisterMaskingEnabled(EL2) SCTLR2MASK_EL2.EMEC == '1' RO When FEAT_MEC is implemented 1 1 1 Reserved, RES0. Otherwise 0 0 0 Reserved, RES0. When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name SCTLR2_EL2 or SCTLR2_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. If FEAT_SRMASK is implemented, accesses to SCTLR2_EL2 are masked by SCTLR2MASK_EL2. MRS <Xt>, SCTLR2_EL2 if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SCTLR2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2_EL2(); end; MSR SCTLR2_EL2, <Xt> if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SCTLR2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLR2_EL2() = X{64}(t); end; MRS <Xt>, SCTLR2_EL1 if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().SCTLR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SCTLR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x278); else X{64}(t) = SCTLR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLR2_EL2(); else X{64}(t) = SCTLR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2_EL1(); end; MSR SCTLR2_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().SCTLR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SCTLR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x278) = X{64}(t); else SCTLR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SCTLR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SCTLR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then SCTLR2_EL2() = X{64}(t); else SCTLR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLR2_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel