SCTLR2_EL3 System Control Register (EL3) when FEAT_SCTLR2 is implemented and FEAT_AA64 is implemented Provides top-level control of the system, including its memory system, at EL3. Other SCTLR2_EL3 is a 64-bit register. 63 12 63:12 Reserved, RES0. CPTM 11 11 0 This field controls Checked Pointer Arithmetic for Multiplication at EL3. If the Effective value of SCTLR2_EL3.CPTA is 0, then the Effective value of this field is 0. 0b0 Pointer Arithmetic for Multiplication is not checked. 0b1 Pointer Arithmetic for Multiplication is checked. '0' When FEAT_CPA2 is implemented 11 11 11 Reserved, RES0. Otherwise 10 10 10 Reserved, RES0. CPTA 9 9 0 This field controls Checked Pointer Arithmetic for Addition at EL3. 0b0 Pointer Arithmetic for Addition is not checked. 0b1 Pointer Arithmetic for Addition is checked. '0' When FEAT_CPA2 is implemented 9 9 9 Reserved, RES0. Otherwise 8 8 8 Reserved, RES0. EnPACM 7 7 0 PACM Enable at EL3. Controls the effect of a PACM instruction at EL3. 0b0 The effects of PACM are disabled at EL3. 0b1 A PACM instruction at EL3 causes PSTATE.PACM to be set to 1. '0' When FEAT_PAuth_LR is implemented 7 7 7 Reserved, RES0. Otherwise 6 5 6:5 Reserved, RES0. EnANERR 4 4 0 Enable Asynchronous Normal Read Error. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate. If FEAT_SVE is implemented, SCTLR2_EL3.EnANERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR. Setting this field to 0 might have a performance impact for Normal memory reads. This field is ignored by the PE and treated as one when all of the following are true: FEAT_ADERR is implemented. ID_AA64MMFR3_EL1.ANERR reads as 0b0010. SCTLR2_EL3.EnADERR is 1. 0b0 External aborts on Normal memory reads generate synchronous Data Abort exceptions in the EL3 translation regime. 0b1 External aborts on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime. '0' When FEAT_ANERR is implemented 4 4 4 Reserved, RES0. Otherwise EnADERR 3 3 0 Enable Asynchronous Device Read Error. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate. If FEAT_SVE is implemented, SCTLR2_EL3.EnADERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR. Setting this field to 0 might have a performance impact for Device memory reads. This field is ignored by the PE and treated as one when all of the following are true: FEAT_ANERR is implemented. ID_AA64MMFR3_EL1.ADERR reads as 0b0010. SCTLR2_EL3.EnANERR is 1. 0b0 External aborts on Device memory reads generate synchronous Data Abort exceptions in the EL3 translation regime. 0b1 External aborts on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime. '0' When FEAT_ADERR is implemented 3 3 3 Reserved, RES0. Otherwise 2 2 2 Reserved, RES0. EMEC 1 1 0 Enables MEC. When enabled, memory accesses to the Realm physical address space are associated with MECID_RL_A_EL3. This bit is permitted to be cached in a TLB. 0b0 MEC is not enabled for the Realm physical address space. 0b1 MEC is enabled for the Realm physical address space. '0' When FEAT_MEC is implemented 1 1 1 Reserved, RES0. Otherwise 0 0 0 Reserved, RES0. MRS <Xt>, SCTLR2_EL3 if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2_EL3(); end; MSR SCTLR2_EL3, <Xt> if !(IsFeatureImplemented(FEAT_SCTLR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().SCTLR2_EL3 == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else SCTLR2_EL3() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel