SCTLR2MASK_EL1 Extended System Control Masking Register (EL1) when FEAT_SRMASK is implemented and FEAT_AA64 is implemented Mask register to prevent updates of fields in SCTLR2_EL1 on writes to SCTLR2_EL1 or SCTLR2ALIAS_EL1. Other SCTLR2MASK_EL1 is a 64-bit register. 63 13 63:13 Reserved, RES0. CPTM0 12 12 0 Mask bit for CPTM0. 0b0 SCTLR2_EL1.CPTM0 is writable. 0b1 SCTLR2_EL1.CPTM0 is not writable. '0' AU When FEAT_CPA2 is implemented 12 12 12 Reserved, RES0. Otherwise CPTM 11 11 0 Mask bit for CPTM. 0b0 SCTLR2_EL1.CPTM is writable. 0b1 SCTLR2_EL1.CPTM is not writable. '0' AU When FEAT_CPA2 is implemented 11 11 11 Reserved, RES0. Otherwise CPTA0 10 10 0 Mask bit for CPTA0. 0b0 SCTLR2_EL1.CPTA0 is writable. 0b1 SCTLR2_EL1.CPTA0 is not writable. '0' AU When FEAT_CPA2 is implemented 10 10 10 Reserved, RES0. Otherwise CPTA 9 9 0 Mask bit for CPTA. 0b0 SCTLR2_EL1.CPTA is writable. 0b1 SCTLR2_EL1.CPTA is not writable. '0' AU When FEAT_CPA2 is implemented 9 9 9 Reserved, RES0. Otherwise EnPACM0 8 8 0 Mask bit for EnPACM0. 0b0 SCTLR2_EL1.EnPACM0 is writable. 0b1 SCTLR2_EL1.EnPACM0 is not writable. '0' AU When FEAT_PAuth_LR is implemented 8 8 8 Reserved, RES0. Otherwise EnPACM 7 7 0 Mask bit for EnPACM. 0b0 SCTLR2_EL1.EnPACM is writable. 0b1 SCTLR2_EL1.EnPACM is not writable. '0' AU When FEAT_PAuth_LR is implemented 7 7 7 Reserved, RES0. Otherwise EnIDCP128 6 6 0 Mask bit for EnIDCP128. 0b0 SCTLR2_EL1.EnIDCP128 is writable. 0b1 SCTLR2_EL1.EnIDCP128 is not writable. '0' AU When FEAT_SYSREG128 is implemented 6 6 6 Reserved, RES0. Otherwise EASE 5 5 0 Mask bit for EASE. 0b0 SCTLR2_EL1.EASE is writable. 0b1 SCTLR2_EL1.EASE is not writable. '0' AU When FEAT_DoubleFault2 is implemented 5 5 5 Reserved, RES0. Otherwise EnANERR 4 4 0 Mask bit for EnANERR. 0b0 SCTLR2_EL1.EnANERR is writable. 0b1 SCTLR2_EL1.EnANERR is not writable. '0' AU When FEAT_ANERR is implemented 4 4 4 Reserved, RES0. Otherwise EnADERR 3 3 0 Mask bit for EnADERR. 0b0 SCTLR2_EL1.EnADERR is writable. 0b1 SCTLR2_EL1.EnADERR is not writable. '0' AU When FEAT_ADERR is implemented 3 3 3 Reserved, RES0. Otherwise NMEA 2 2 0 Mask bit for NMEA. 0b0 SCTLR2_EL1.NMEA is writable. 0b1 SCTLR2_EL1.NMEA is not writable. '0' AU When FEAT_DoubleFault2 is implemented 2 2 2 Reserved, RES0. Otherwise 1 0 1:0 Reserved, RES0. When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SCTLR2MASK_EL1 or SCTLR2MASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, SCTLR2MASK_EL1 if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nSCTLR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x328); else X{64}(t) = SCTLR2MASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLR2MASK_EL2(); else X{64}(t) = SCTLR2MASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR2MASK_EL1(); end; MSR SCTLR2MASK_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nSCTLR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x328) = X{64}(t); elsif !IsZero(SCTLR2MASK_EL1()) then Undefined(); else SCTLR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(SCTLR2MASK_EL2()) then Undefined(); else SCTLR2MASK_EL2() = X{64}(t); end; else SCTLR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLR2MASK_EL1() = X{64}(t); end; MRS <Xt>, SCTLR2MASK_EL12 When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x328); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SCTLR2MASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = SCTLR2MASK_EL1(); else Undefined(); end; end; MSR SCTLR2MASK_EL12, <Xt> When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x328) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SCTLR2MASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SCTLR2MASK_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel