SCTLR_EL1
System Control Register (EL1)
when FEAT_AA64 is implemented
SCTLR
Architectural
AArch32
31
0
31
0
31
0
31
0
Provides top-level control of the system, including its memory system, at EL1 and EL0.
Other
SCTLR_EL1 is a 64-bit register.
TIDCP
63
63
0
Trap IMPLEMENTATION DEFINED functionality. When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps EL0 accesses to the encodings reserved for IMPLEMENTATION DEFINED functionality to EL1.
0b0
No instructions accessing the System register or System instruction spaces are trapped by this mechanism.
0b1
Instructions accessing the following System register or System instruction spaces are trapped to EL1 by this mechanism:
In AArch64 state, EL0 access to the encodings in the following reserved encoding spaces are trapped:
IMPLEMENTATION DEFINED System instructions, which are accessed using SYS and SYSL, with CRn == {11, 15}, and are reported using EC syndrome value 0x18.
IMPLEMENTATION DEFINED System instructions, which are accessed using SYSP, with CRn == {11, 15}, and are reported using EC syndrome value 0x14.
IMPLEMENTATION DEFINED System registers, which are accessed using MRS and MSR with the S3_<op1>_<Cn>_<Cm>_<op2> register name, and are reported using EC syndrome value 0x18.
IMPLEMENTATION DEFINED System registers, which are accessed using MRRS and MSRR with the S3_<op1>_<Cn>_<Cm>_<op2> register name, and are reported using EC syndrome value 0x14.
In AArch32 state, EL0 MCR and MRC access to the following encodings are trapped and reported using EC syndrome value 0x03:
All coproc==p15, CRn==c9, opc1 == {0-7}, CRm == {c0-c2, c5-c8}, opc2 == {0-7}.
All coproc==p15, CRn==c10, opc1 =={0-7}, CRm == {c0, c1, c4, c8}, opc2 == {0-7}.
All coproc==p15, CRn==c11, opc1=={0-7}, CRm == {c0-c8, c15}, opc2 == {0-7}.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TIDCP == '1'
RO
When FEAT_TIDCP1 is implemented
63
63
63
Reserved, RES0.
Otherwise
SPINTMASK
62
62
0
SP Interrupt Mask enable. When SCTLR_EL1.NMI is 1, controls whether PSTATE.SP acts as an interrupt mask, and controls the value of PSTATE.ALLINT on taking an exception to EL1.
0b0
Does not cause PSTATE.SP to mask interrupts.
PSTATE.ALLINT is set to 1 on taking an exception to EL1.
0b1
When PSTATE.SP is 1 and execution is at EL1, an IRQ or FIQ interrupt that is targeted to EL1 is masked regardless of any indication of Superpriority.
PSTATE.ALLINT is set to 0 on taking an exception to EL1.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.SPINTMASK == '1'
RO
When FEAT_NMI is implemented
62
62
62
Reserved, RES0.
Otherwise
NMI
61
61
0
Non-maskable Interrupt enable.
0b0
This control does not affect interrupt masking behavior.
0b1
This control enables all of the following:
The use of the PSTATE.ALLINT interrupt mask.
IRQ and FIQ interrupts to have Superpriority as an additional attribute.
PSTATE.SP to be used as an interrupt mask.
'0'
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.NMI == '1'
RO
When FEAT_NMI is implemented
61
61
61
Reserved, RES0.
Otherwise
EnTP2
60
60
0
Traps instructions executed at EL0 that access TPIDR2_EL0 to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1. The exception is reported using EC syndrome value 0x18.
If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field has no effect on execution at EL0.
0b0
This control causes execution of these instructions at EL0 to be trapped.
0b1
This control does not cause execution of any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnTP2 == '1'
RO
When FEAT_SME is implemented
60
60
60
Reserved, RES0.
Otherwise
TCSO
59
59
0
Tag Checking Store Only.
0b0
This field has no effect on Tag checking.
0b1
Explicit Memory Read Effects generated by instructions executed in EL1 are Tag Unchecked.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TCSO == '1'
RO
When FEAT_MTE_STORE_ONLY is implemented
59
59
59
Reserved, RES0.
Otherwise
TCSO0
58
58
0
When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, Tag Checking Store Only in EL0.
0b0
This field has no effect on Tag checking.
0b1
Explicit Memory Read Effects generated by instructions executed in EL0 are Tag Unchecked.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TCSO0 == '1'
RO
When FEAT_MTE_STORE_ONLY is implemented
58
58
58
Reserved, RES0.
Otherwise
EPAN
57
57
0
Enhanced Privileged Access Never. When PSTATE.PAN is 1, determines whether an EL1 data access to a page with stage 1 EL0 instruction access permission generates a Permission fault as a result of the Privileged Access Never mechanism.
This bit is permitted to be cached in a TLB.
0b0
No additional Permission faults are generated by this mechanism.
0b1
An EL1 data access to a page with stage 1 EL0 data access permission or stage 1 EL0 instruction access permission generates a Permission fault.
Any speculative data accesses that would generate a Permission fault as a result of PSTATE.PAN = 1 if the accesses were not speculative, will not cause an allocation into a cache.
When executing at EL1, this does not prevent unprivileged speculative accesses generated from the EL0 hardware-defined context from causing allocation into a cache.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EPAN == '1'
RO
When FEAT_PAN3 is implemented
57
57
57
Reserved, RES0.
Otherwise
EnALS
56
56
0
When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an LD64B or ST64B instruction at EL0 to EL1.
A trap of an LD64B or ST64B instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000002.
0b0
Execution of an LD64B or ST64B instruction at EL0 is trapped to EL1.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnALS == '1'
RO
When FEAT_LS64 is implemented
56
56
56
Reserved, RES0.
Otherwise
EnAS0
55
55
0
When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV0 instruction at EL0 to EL1.
A trap of an ST64BV0 instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000001.
0b0
Execution of an ST64BV0 instruction at EL0 is trapped to EL1.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnAS0 == '1'
RO
When FEAT_LS64_ACCDATA is implemented
55
55
55
Reserved, RES0.
Otherwise
EnASR
54
54
0
When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV instruction at EL0 to EL1.
A trap of an ST64BV instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000000.
0b0
Execution of an ST64BV instruction at EL0 is trapped to EL1.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnASR == '1'
RO
When FEAT_LS64_V is implemented
54
54
54
Reserved, RES0.
Otherwise
53
50
53:50
Reserved, RES0.
TWEDEL
49
46
3:0
TWE Delay. A 4-bit unsigned number that, when SCTLR_EL1.TWEDEn is 1, encodes the minimum delay in taking a trap of WFE* caused by SCTLR_EL1.nTWE as 2(TWEDEL + 8) cycles.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TWEDEL == '1'
RO
When FEAT_TWED is implemented
49
46
49:46
Reserved, RES0.
Otherwise
TWEDEn
45
45
0
TWE Delay Enable. Enables a configurable delayed trap of the WFE* instruction caused by SCTLR_EL1.nTWE.
0b0
The delay for taking the trap is IMPLEMENTATION DEFINED.
0b1
The delay for taking the trap is at least the number of cycles defined in SCTLR_EL1.TWEDEL.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TWEDEn == '1'
RO
When FEAT_TWED is implemented
45
45
45
Reserved, RES0.
Otherwise
DSSBS
44
44
0
Default PSTATE.SSBS value on Exception Entry.
0b0
PSTATE.SSBS is set to 0 on an exception to EL1.
0b1
PSTATE.SSBS is set to 1 on an exception to EL1.
ID
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.DSSBS == '1'
RO
When FEAT_SSBS is implemented
44
44
44
Reserved, RES0.
Otherwise
ATA
43
43
0
Allocation Tag Access at EL1.
Controls use of Memory tagging at EL1.
The Effective value of this field is 0 if any of the following are true:
The Effective value of SCR_EL3.ATA is 0.
The Effective value of HCR_EL2.ATA is 0.
0b0
Use of Memory tagging is disabled at EL1.
0b1
Use of Memory tagging is enabled at EL1.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.ATA == '1'
RO
When FEAT_MTE2 is implemented
43
43
43
Reserved, RES0.
Otherwise
ATA0
42
42
0
Allocation Tag Access at EL0.
Controls access to Allocation Tags and Tag Check operations at EL0 when HCR_EL2,{E2H,TGE} is not {1,1}.
The Effective value of this field is 0 if any of the following are true:
The Effective value of SCR_EL3.ATA is 0.
The Effective value of HCR_EL2.ATA is 0.
Software may change this control bit on a context switch.
0b0
Use of Memory tagging is disabled at EL0.
0b1
Use of Memory tagging is enabled at EL0.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.ATA0 == '1'
RO
When FEAT_MTE2 is implemented
42
42
42
Reserved, RES0.
Otherwise
TCF
41
40
1:0
Tag Check Fault at EL1. Controls the effect of Tag Check Faults due to Loads and Stores at EL1.
If FEAT_MTE3 is not implemented, the value 0b11 is reserved.
0b00
Tag Check Faults have no effect on the PE.
0b01
Tag Check Faults cause a synchronous exception.
0b10
Tag Check Faults are asynchronously accumulated.
0b11
Tag Check Faults cause a synchronous exception on reads, and are asynchronously accumulated on writes.
When FEAT_MTE_ASYM_FAULT is implemented
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TCF == '1'
RO
When FEAT_MTE2 is implemented
41
40
41:40
Reserved, RES0.
Otherwise
TCF0
39
38
1:0
Tag Check Fault at EL0. When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, controls the effect of Tag Check Faults due to Loads and Stores at EL0.
If FEAT_MTE3 is not implemented, the value 0b11 is reserved.
Software may change this control bit on a context switch.
0b00
Tag Check Faults have no effect on the PE.
0b01
Tag Check Faults cause a synchronous exception.
0b10
Tag Check Faults are asynchronously accumulated.
0b11
Tag Check Faults cause a synchronous exception on reads, and are asynchronously accumulated on writes.
When FEAT_MTE_ASYM_FAULT is implemented
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TCF0 == '1'
RO
When FEAT_MTE2 is implemented
39
38
39:38
Reserved, RES0.
Otherwise
ITFSB
37
37
0
When synchronous exceptions are not being generated by Tag Check Faults, this field controls whether on exception entry into EL1, all Tag Check Faults due to instructions executed before exception entry, that are reported asynchronously, are synchronized into TFSRE0_EL1 and TFSR_EL1 registers.
0b0
Tag Check Faults are not synchronized on entry to EL1.
0b1
Tag Check Faults are synchronized on entry to EL1.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.ITFSB == '1'
RO
When FEAT_MTE_ASYNC is implemented
37
37
37
Reserved, RES0.
Otherwise
BT1
36
36
0
Configures the Branch Type compatibility of the implicit BTI behavior for the following instructions at EL1:
PACIASP.
PACIBSP.
If FEAT_PAuth_LR is implemented, PACIASPPC.
If FEAT_PAuth_LR is implemented, PACIBSPPC.
0b0
When the PE is executing at EL1, when the specified instructions have an implicit BTI behavior, they are compatible with the same BTYPE values as BTI.jc.
0b1
When the PE is executing at EL1, when the specified instructions have an implicit BTI behavior, they are compatible with the same BTYPE values as BTI.c.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.BT1 == '1'
RO
When FEAT_BTI is implemented
36
36
36
Reserved, RES0.
Otherwise
BT0
35
35
0
Configures the Branch Type compatibility of the implicit BTI behavior for the following instructions at EL0:
PACIASP.
PACIBSP.
If FEAT_PAuth_LR is implemented, PACIASPPC.
If FEAT_PAuth_LR is implemented, PACIBSPPC.
When the value of the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the value of SCTLR_EL1.BT0 has no effect on execution at EL0.
0b0
When the PE is executing at EL0, when the specified instructions have an implicit BTI behavior, they are compatible with the same BTYPE values as BTI.jc.
0b1
When the PE is executing at EL0, when the specified instructions have an implicit BTI behavior, they are compatible with the same BTYPE values as BTI.c.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.BT0 == '1'
RO
When FEAT_BTI is implemented
35
35
35
Reserved, RES0.
Otherwise
EnFPM
34
34
0
Enables direct and indirect accesses to FPMR from EL0.
When accesses to FPMR are disabled by this control:
Direct accesses to FPMR from EL0 are trapped to EL1, or to EL2 when EL2 is implemented and enabled in the current Security state and HCR_EL2.TGE is 1. These exceptions are reported using EC syndrome value 0x18.
Execution of FP8 data-processing instructions that indirectly access FPMR is UNDEFINED at EL0.
Traps are not taken if there is a higher priority exception generated by the access.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0, and the SCTLR_EL2.EnFPM control is used for this purpose.
0b0
Direct and indirect accesses to FPMR are disabled at EL0.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnFPM == '1'
RO
When FEAT_FPMR is implemented
34
34
34
Reserved, RES0.
Otherwise
MSCEn
33
33
0
Memory Copy and Memory Set instructions Enable. Enables execution of the Memory Copy and Memory Set instructions at EL0.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the Effective value of this bit is 1.
0b0
Execution of the Memory Copy and Memory Set instructions is UNDEFINED at EL0.
0b1
This control does not cause any instructions to be UNDEFINED.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.MSCEn == '1'
RO
When FEAT_MOPS is implemented
33
33
33
Reserved, RES0.
Otherwise
CMOW
32
32
0
Controls the required permissions for the following cache maintenance instructions executed at EL0:
Any DC instruction that operates by VA and performs a clean and invalidate operation.
Any IC instruction that operates by VA.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
For more information, see:
Stage 1 permissions.
Implications of enabling the dirty state management mechanism.
This bit is permitted to be cached in a TLB.
0b0
This control does not cause any instruction to generate a stage 1 Permission fault.
0b1
For these instructions, when executed at EL0, the absence of stage 1 unprivileged write permission generates a stage 1 permission fault.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.CMOW == '1'
RO
When FEAT_CMOW is implemented
32
32
32
Reserved, RES0.
Otherwise
EnIA
31
31
0
Controls enabling of pointer authentication of instruction addresses, using the APIAKey_EL1 key, at EL1 and at EL0 in the EL1&0 translation regime.
This field controls the behavior of the AddPACIA() and AuthIA() pseudocode functions. When pointer authentication is enabled, AddPACIA() returns a copy of a pointer to which a pointer authentication code has been added, and AuthIA() returns an authenticated copy of a pointer. When pointer authentication is disabled, both of these functions are NOP.
0b0
Pointer authentication of instruction addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APIAKey_EL1 key, is not enabled.
0b1
Pointer authentication of instruction addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APIAKey_EL1 key, is enabled.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnIA == '1'
RO
When FEAT_PAuth is implemented
31
31
31
Reserved, RES0.
Otherwise
EnIB
30
30
0
Controls enabling of pointer authentication of instruction addresses, using the APIBKey_EL1 key, at EL1 and at EL0 in the EL1&0 translation regime.
This field controls the behavior of the AddPACIB() and AuthIB() pseudocode functions. When pointer authentication is enabled, AddPACIB() returns a copy of a pointer to which a pointer authentication code has been added, and AuthIB() returns an authenticated copy of a pointer. When pointer authentication is disabled, both of these functions are NOP.
0b0
Pointer authentication of instruction addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APIBKey_EL1 key, is not enabled.
0b1
Pointer authentication of instruction addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APIBKey_EL1 key, is enabled.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnIB == '1'
RO
When FEAT_PAuth is implemented
30
30
30
Reserved, RES0.
Otherwise
LSMAOE
29
29
0
Load Multiple and Store Multiple Atomicity and Ordering Enable.
This bit is permitted to be cached in a TLB.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
For all memory accesses at EL0, T32 and A32 Load Multiple and Store Multiple can have an interrupt taken during the sequence memory accesses, and the memory accesses are not required to be ordered.
0b1
The ordering and interrupt behavior of T32 and A32 Load Multiple and Store Multiple at EL0 is as defined for Armv8.0.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.LSMAOE == '1'
RO
When FEAT_LSMAOC is implemented
29
29
29
Reserved, RES1.
Otherwise
nTLSMD
28
28
0
No Trap Load Multiple and Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory.
This bit is permitted to be cached in a TLB.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
All memory accesses by T32 and A32 Load Multiple and Store Multiple at EL0 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are trapped and generate a stage 1 Alignment fault.
0b1
All memory accesses by T32 and A32 Load Multiple and Store Multiple at EL0 that are marked at stage 1 as Device-nGRE/Device-nGnRE/Device-nGnRnE memory are not trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.nTLSMD == '1'
RO
When FEAT_LSMAOC is implemented
28
28
28
Reserved, RES1.
Otherwise
EnDA
27
27
0
Controls enabling of pointer authentication of data addresses, using the APDAKey_EL1 key, at EL1 and at EL0 in the EL1&0 translation regime.
This field controls the behavior of the AddPACDA() and AuthDA() pseudocode functions. When pointer authentication is enabled, AddPACDA() returns a copy of a pointer to which a pointer authentication code has been added, and AuthDA() returns an authenticated copy of a pointer. When pointer authentication is disabled, both of these functions are NOP.
0b0
Pointer authentication of data addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APDAKey_EL1 key, is not enabled.
0b1
Pointer authentication of data addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APDAKey_EL1 key, is enabled.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnDA == '1'
RO
When FEAT_PAuth is implemented
27
27
27
Reserved, RES0.
Otherwise
UCI
26
26
26
Traps EL0 execution of cache maintenance instructions, to EL1, or to EL2 when it is implemented and enabled in the current Security state and HCR_EL2.TGE is 1, from AArch64 state only, reported using EC syndrome value 0x18, as follows:
DC CVAU, DC CIVAC, DC CVAC, and IC IVAU.
If FEAT_MTE is implemented, DC CIGVAC, DC CIGDVAC, DC CGVAC, and DC CGDVAC.
If FEAT_DPB is implemented, DC CVAP.
If FEAT_DPB and FEAT_MTE are implemented, DC CGVAP and DC CGDVAP.
If FEAT_DPB2 is implemented, DC CVADP.
If FEAT_DPB2 and FEAT_MTE are implemented, DC CGVADP and DC CGDVADP.
If FEAT_OCCMO is implemented, DC CIVAOC, DC CIGDVAOC, DC CVAOC and DC CGDVAOC.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
For each of the specified instructions, if the execution of the instruction can be trapped, access at EL0 using AArch64 is trapped.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.UCI == '1'
RO
EE
25
25
0
Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime.
The EE bit is permitted to be cached in a TLB.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
0b0
Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are little-endian.
0b1
Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are big-endian.
ID
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EE == '1'
RO
When FEAT_MixedEnd is implemented
25
25
0
Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are big-endian.
Reserved, RES1.
When FEAT_BigEnd is implemented
25
25
0
Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are little-endian.
Reserved, RES0.
Otherwise
E0E
24
24
0
Endianness of data accesses at EL0.
This bit has no effect on the endianness of Explicit Memory Effects generated by unprivileged memory access instructions executed at EL1.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
Explicit data accesses at EL0 are little-endian.
0b1
Explicit data accesses at EL0 are big-endian.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.E0E == '1'
RO
When FEAT_MixedEndEL0 is implemented
24
24
0
Explicit data accesses at EL0 are big-endian.
Reserved, RES1.
When FEAT_BigEndEL0 is implemented
24
24
0
Explicit data accesses at EL0 are little-endian.
Reserved, RES0.
Otherwise
SPAN
23
23
0
Set Privileged Access Never, on taking an exception to EL1.
0b0
PSTATE.PAN is set to 1 on taking an exception to EL1.
0b1
The value of PSTATE.PAN is left unchanged on taking an exception to EL1.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.SPAN == '1'
RO
When FEAT_PAN is implemented
23
23
23
Reserved, RES1.
Otherwise
EIS
22
22
0
Exception Entry is a context synchronization event.
If SCTLR_EL1.EIS is 0:
Indirect writes to ESR_EL1, FAR_EL1, SPSR_EL1, ELR_EL1 are synchronized on exception entry to EL1, so that a direct read of the register after exception entry sees the indirectly written value caused by the exception entry.
Memory transactions, including instruction fetches, from an Exception level always use the translation resources associated with that translation regime.
Exception Catch debug events are synchronous debug events.
DCPS* and DRPS instructions are context synchronization events.
Some exception entries reported are not considered IFBEs per the memory model.
The following are not affected by the value of SCTLR_EL1.EIS:
Changes to the PSTATE information on entry to EL1.
Behavior of accessing the banked copies of the stack pointer using the SP register name for loads, stores and data processing instructions.
The memory model requirement for exception entry to generate an Instruction Fetch Barrier Effect for some exception entries. See Basic definitions for the list of exception entries.
Exit from Debug state.
0b0
The taking of an exception to EL1 is not a context synchronization event.
0b1
The taking of an exception to EL1 is a context synchronization event.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EIS == '1'
RO
When FEAT_ExS is implemented
22
22
22
Reserved, RES1.
Otherwise
IESB
21
21
0
Implicit Error Synchronization event enable. Possible values are:
If FEAT_DoubleFault2 is implemented, the PE is in Non-debug state, and the Effective value of SCTLR2_EL1.NMEA is 1, then SCTLR_EL1.IESB is ignored and the PE behaves as if SCTLR_EL1.IESB is 1 for all purposes other than direct read of the register.
The value of this field is ignored in Debug state and treated as zero.
0b0
Disabled.
0b1
An implicit error synchronization event is added:
At each exception taken to EL1.
Before the operational pseudocode of each Exception Return instruction executed at EL1.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.IESB == '1'
RO
When FEAT_IESB is implemented
21
21
21
Reserved, RES0.
Otherwise
TSCXT
20
20
0
Trap EL0 Access to the SCXTNUM_EL0 register, when EL0 is using AArch64.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
EL0 access to SCXTNUM_EL0 is not disabled by this mechanism.
0b1
EL0 access to SCXTNUM_EL0 is disabled, causing an exception to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1.
The value of SCXTNUM_EL0 is treated as 0.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.TSCXT == '1'
RO
When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented
20
20
20
Reserved, RES1.
Otherwise
WXN
19
19
19
Write permission implies XN (Execute-never). For the EL1&0 translation regime, this bit can restrict execute permissions on writable pages.
This bit applies only when SCTLR_EL1.M bit is set.
The WXN bit is permitted to be cached in a TLB.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
This field is RES0 if TCR2_EL1.PIE is 1.
0b0
This control has no effect on memory access permissions.
0b1
In the EL1&0 translation regime, any region of memory that is writable at EL1 is XN at EL1, and any region of memory that is writable at EL0 is XN at EL0.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.WXN == '1'
RO
nTWE
18
18
18
Traps EL0 execution of WFE instructions to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from both Execution states, reported using EC syndrome value 0x01.
When FEAT_WFxT is implemented, this trap also applies to the WFET instruction.
In AArch32 state, the attempted execution of a conditional WFE instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
Any attempt to execute a WFE instruction at EL0 is trapped, if the instruction would otherwise have caused the PE to enter a low-power state.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.nTWE == '1'
RO
17
17
17
Reserved, RES0.
nTWI
16
16
16
Traps EL0 execution of WFI instructions to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from both Execution states, reported using EC syndrome value 0x01.
When FEAT_WFxT is implemented, this trap also applies to the WFIT instruction.
In AArch32 state, the attempted execution of a conditional WFI instruction is only trapped if the instruction passes its condition code check.
Since a WFE or WFI can complete at any time, even without a Wakeup event, the traps on WFE of WFI are not guaranteed to be taken, even if the WFE or WFI is executed when there is no Wakeup event. The only guarantee is that if the instruction does not complete in finite time in the absence of a Wakeup event, the trap will be taken.When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
Any attempt to execute a WFI instruction at EL0 is trapped, if the instruction would otherwise have caused the PE to enter a low-power state.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.nTWI == '1'
RO
UCT
15
15
15
Traps EL0 accesses to the CTR_EL0 to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from AArch64 state only, reported using EC syndrome value 0x18.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
Accesses to the CTR_EL0 from EL0 using AArch64 are trapped.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.UCT == '1'
RO
DZE
14
14
14
Traps EL0 execution of DC ZVA instructions to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from AArch64 state only, reported using EC syndrome value 0x18.
If FEAT_MTE is implemented, this trap also applies to DC GVA and DC GZVA.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
Any attempt to execute an instruction that this trap applies to at EL0 using AArch64 is trapped.
Reading DCZID_EL0.DZP from EL0 returns 1, indicating that the instructions this trap applies to are not supported.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.DZE == '1'
RO
EnDB
13
13
0
Controls enabling of pointer authentication of data addresses, using the APDBKey_EL1 key, at EL1 and at EL0 in the EL1&0 translation regime.
This field controls the behavior of the AddPACDB() and AuthDB() pseudocode functions. When pointer authentication is enabled, AddPACDB() returns a copy of a pointer to which a pointer authentication code has been added, and AuthDB() returns an authenticated copy of a pointer. When pointer authentication is disabled, both of these functions are NOP.
0b0
Pointer authentication of data addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APDBKey_EL1 key, is not enabled.
0b1
Pointer authentication of data addresses at EL1 and at EL0 in the EL1&0 translation regime, using the APDBKey_EL1 key, is enabled.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnDB == '1'
RO
When FEAT_PAuth is implemented
13
13
13
Reserved, RES0.
Otherwise
I
12
12
12
Stage 1 instruction access Cacheability control, for accesses at EL0 and EL1:
When the value of the HCR_EL2.DC bit is 1, then instruction access to Normal memory from EL0 and EL1 are Cacheable regardless of the value of the SCTLR_EL1.I bit.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
0b0
All instruction access to Stage 1 Normal memory from EL0 and EL1 are Stage 1 Non-cacheable.
If the value of SCTLR_EL1.M is 0, instruction accesses from stage 1 of the EL1&0 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory.
0b1
This control has no effect on the Stage 1 Cacheability of instruction access to Stage 1 Normal memory from EL0 and EL1.
If the value of SCTLR_EL1.M is 0, instruction accesses from stage 1 of the EL1&0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory.
'0'
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.I == '1'
RO
EOS
11
11
0
Exception Exit is a context synchronization event.
If SCTLR_EL1.EOS is set to 0:
Memory transactions, including instruction fetches, from an Exception level always use the translation resources associated with that translation regime.
Exception Catch debug events are synchronous debug events.
DCPS* and DRPS instructions are context synchronization events.
The following are not affected by the value of SCTLR_EL1.EOS:
The indirect write of the PSTATE and PC values from SPSR_EL1 and ELR_EL1 on exception return is synchronized.
Behavior of accessing the banked copies of the stack pointer using the SP register name for loads, stores and data processing instructions.
Exit from Debug state.
0b0
An exception return from EL1 is not a context synchronization event
0b1
An exception return from EL1 is a context synchronization event
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EOS == '1'
RO
When FEAT_ExS is implemented
11
11
11
Reserved, RES1.
Otherwise
EnRCTX
10
10
0
Enable EL0 access to the following System instructions:
CFPRCTX, DVPRCTX and CPPRCTX instructions.
If FEAT_SPECRES2 is implemented, COSPRCTX.
CFP RCTX, DVP RCTX and CPP RCTX instructions.
If FEAT_SPECRES2 is implemented, COSP RCTX.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
EL0 access to these instructions is disabled, and these instructions are trapped to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1.
0b1
EL0 access to these instructions is enabled.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.EnRCTX == '1'
RO
When FEAT_SPECRES is implemented
10
10
10
Reserved, RES0.
Otherwise
UMA
9
9
9
User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from AArch64 state only, reported using EC syndrome value 0x18.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the value of this bit is treated as 0 for all purposes other than reading the value of the register.
0b0
Any attempt at EL0 using AArch64 to execute an MRS, MSR(register), or MSR(immediate) instruction that accesses the DAIF is trapped.
0b1
This control does not cause any instructions to be trapped.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.UMA == '1'
RO
SED
8
8
0
SETEND instruction disable. Disables SETEND instructions at EL0 using AArch32.
If the implementation does not support mixed-endian operation at any Exception level, this bit is RES1.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
SETEND instruction execution is enabled at EL0 using AArch32.
0b1
SETEND instructions are UNDEFINED at EL0 using AArch32 and any attempt at EL0 to access a SETEND instruction generates an exception to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, reported using EC syndrome value 0x00.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.SED == '1'
RO
When FEAT_AA32EL0 is implemented
8
8
8
Reserved, RES1.
Otherwise
ITD
7
7
0
IT Disable. Disables some uses of IT instructions at EL0 using AArch32.
If an instruction in an active IT block that would be disabled by this field sets this field to 1, then behavior is CONSTRAINED UNPREDICTABLE. For more information, see 'Changes to an ITD control by an instruction in an IT block'.
ITD is optional, but if it is implemented in the SCTLR_EL1, then it must also be implemented in the SCTLR_EL2, HSCTLR, and SCTLR.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
All IT instruction functionality is enabled at EL0 using AArch32.
0b1
Any attempt at EL0 using AArch32 to execute any of the following is UNDEFINED and generates an exception, reported using EC syndrome value 0x00, to EL1 or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1:
All encodings of the IT instruction with hw1[3:0]!=1000.
All encodings of the subsequent instruction with the following values for hw1:
0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit instructions B, UDF, SVC, LDM, and STM.
0b1011xxxxxxxxxxxx: All instructions in 'Miscellaneous 16-bit instructions'.
0b10100xxxxxxxxxxx: ADD Rd, PC, #imm
0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX PC; BLX PC.
0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This pattern also covers unpredictable cases with BLX Rn.
These instructions are always UNDEFINED, regardless of whether they would pass or fail the condition code check that applies to them as a result of being in an IT block.
It is IMPLEMENTATION DEFINED whether the IT instruction is treated as:
A 16-bit instruction, that can only be followed by another 16-bit instruction.
The first half of a 32-bit instruction.
This means that, for the situations that are UNDEFINED, either the second 16-bit instruction or the 32-bit instruction is UNDEFINED.
An implementation might vary dynamically as to whether IT is treated as a 16-bit instruction or the first half of a 32-bit instruction.
AU
When an implementation does not implement ITD
RAZ/WI
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.ITD == '1'
RO
When FEAT_AA32EL0 is implemented
7
7
7
Reserved, RES1.
Otherwise
nAA
6
6
0
Non-aligned access. This bit controls generation of Alignment faults at EL1 and EL0 under certain conditions.
The following instructions generate an Alignment fault if all bytes being accessed are not within a single naturally aligned 16-byte quantity, for access:
LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH, LDLAR, LDLARH.
STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH.
If FEAT_LRCPC3 is implemented, the post index versions of LDAPR and the pre index versions of STLR.
If FEAT_LRCPC3 and Advanced SIMD and floating-point instructions are implemented, LDAPUR (SIMD&FP), LDAP1 (SIMD&FP), STLUR (SIMD&FP), and STL1 (SIMD&FP).
If FEAT_LRCPC3 is implemented, the following instructions generate an Alignment fault if all bytes being accessed for a single register are not within a single naturally aligned 16-byte quantity, for access:
LDIAPP, STILP.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
For a load-acquire instruction that does not have acquire semantics as the result of the destination register, or registers, being ZR, it is IMPLEMENTATION SPECIFIC whether this field behaves as 1 or the programmed value.
0b0
Unaligned accesses by the specified instructions generate an Alignment fault.
0b1
This control does not generate Alignment faults.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.nAA == '1'
RO
When FEAT_LSE2 is implemented
6
6
6
Reserved, RES0.
Otherwise
CP15BEN
5
5
0
System instruction memory barrier enable. Enables accesses to the DMB, DSB, and ISB System instructions in the (coproc==0b1111) encoding space from EL0:
CP15BEN is optional, but if it is implemented in the SCTLR_EL1, then it must also be implemented in the SCTLR_EL2, HSCTLR, and SCTLR.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
0b0
EL0 using AArch32: EL0 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is UNDEFINED and generates an exception to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1. The exception is reported using EC syndrome value 0x00.
0b1
EL0 using AArch32: EL0 execution of the CP15DMB, CP15DSB, and CP15ISB instructions is enabled.
AU
When an implementation does not implement CP15BEN
RAO/WI
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.CP15BEN == '1'
RO
When FEAT_AA32EL0 is implemented
5
5
5
Reserved, RES0.
Otherwise
SA0
4
4
4
SP Alignment check enable for EL0. When set to 1, if a load or store instruction executed at EL0 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then an SP alignment fault exception is generated. For more information, see 'SP alignment checking'.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.SA0 == '1'
RO
SA
3
3
3
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL1 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then an SP alignment fault exception is generated. For more information, see 'SP alignment checking'.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.SA == '1'
RO
C
2
2
2
Stage 1 Cacheability control, for data accesses.
When the Effective value of the HCR_EL2.DC bit in the current Security state is 1, the PE ignores SCTLR_EL1.C. This means that EL0 and EL1 data accesses to Normal memory are Cacheable.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
0b0
All data access to Stage 1 Normal memory from EL0 and EL1, and all Normal memory accesses from unified cache to the EL1&0 Stage 1 translation tables, are treated as Stage 1 Non-cacheable.
0b1
This control has no effect on the Stage 1 Cacheability of:
Data access to Normal memory from EL0 and EL1.
Normal memory accesses to the EL1&0 Stage 1 translation tables.
'0'
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.C == '1'
RO
A
1
1
1
Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the value of this bit is treated as 0 for all purposes other than reading the value of the register.
0b0
Alignment fault checking is disabled when executing at EL1 or EL0.
Alignment checks on some instructions are not disabled by this control. For more information, see 'Alignment of data accesses'.
0b1
Alignment fault checking is enabled when executing at EL1 or EL0.
All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception.
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.A == '1'
RO
M
0
0
0
MMU enable for EL1&0 stage 1 address translation.
If the Effective value of HCR_EL2.{DC, TGE} in the current Security state is not {0, 0}, then the PE behaves as if the value of the SCTLR_EL1.M field is 0 for all purposes other than returning the value of a direct read of the field.
When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
0b0
EL1&0 stage 1 address translation disabled.
See the SCTLR_EL1.I field for the behavior of instruction accesses to Normal memory.
0b1
EL1&0 stage 1 address translation enabled.
'0'
AU
FEAT_SRMASK is implemented
EL1 is the current Exception level
IsSystemRegisterMaskingEnabled(EL1)
SCTLRMASK_EL1.M == '1'
RO
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SCTLR_EL1 or SCTLR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name.
If FEAT_SRMASK is implemented, accesses to SCTLR_EL1 are masked by SCTLRMASK_EL1.
MRS <Xt>, SCTLR_EL1
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2().TRVM == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().SCTLR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
X{64}(t) = NVMem(0x110);
else
X{64}(t) = SCTLR_EL1();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
X{64}(t) = SCTLR_EL2();
else
X{64}(t) = SCTLR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = SCTLR_EL1();
end;
MSR SCTLR_EL1, <Xt>
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2().TVM == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().SCTLR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
NVMem(0x110) = X{64}(t);
else
SCTLR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
SCTLR_EL2() = X{64}(t);
else
SCTLR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
SCTLR_EL1() = X{64}(t);
end;
MRS <Xt>, SCTLR_EL12
When FEAT_VHE is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
X{64}(t) = NVMem(0x110);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
X{64}(t) = SCTLR_EL1();
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
X{64}(t) = SCTLR_EL1();
else
Undefined();
end;
end;
MSR SCTLR_EL12, <Xt>
When FEAT_VHE is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() == '101' then
NVMem(0x110) = X{64}(t);
elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x18);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
SCTLR_EL1() = X{64}(t);
else
Undefined();
end;
elsif PSTATE.EL == EL3 then
if ELIsInHost(EL2) then
SCTLR_EL1() = X{64}(t);
else
Undefined();
end;
end;
MRS <Xt>, SCTLRALIAS_EL1
When FEAT_SRMASK is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2().TRVM == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nSCTLRALIAS_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
X{64}(t) = NVMem(0x110);
else
X{64}(t) = SCTLR_EL1();
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
X{64}(t) = SCTLR_EL2();
else
X{64}(t) = SCTLR_EL1();
end;
elsif PSTATE.EL == EL3 then
X{64}(t) = SCTLR_EL1();
end;
MSR SCTLRALIAS_EL1, <Xt>
When FEAT_SRMASK is implemented
if !IsFeatureImplemented(FEAT_AA64) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2().TVM == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nSCTLRALIAS_EL1 == '0') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EffectiveHCR_EL2_NVx() IN {'111'} then
NVMem(0x110) = X{64}(t);
else
SCTLR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if ELIsInHost(EL2) then
SCTLR_EL2() = X{64}(t);
else
SCTLR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
SCTLR_EL1() = X{64}(t);
end;
2026-03-26 20:27:25
2026-03_rel