SCTLR_EL3 System Control Register (EL3) when EL3 is implemented and FEAT_AA64 is implemented Provides top-level control of the system, including its memory system, at EL3. Other SCTLR_EL3 is a 64-bit register. 63 63 63 Reserved, RES0. SPINTMASK 62 62 0 SP Interrupt Mask enable. When SCTLR_EL3.NMI is 1, controls whether PSTATE.SP acts as an interrupt mask, and controls the value of PSTATE.ALLINT on taking an exception to EL3. 0b0 Does not cause PSTATE.SP to mask interrupts. PSTATE.ALLINT is set to 1 on taking an exception to EL3. 0b1 When PSTATE.SP is 1 and execution is at EL3, an IRQ or FIQ interrupt that is targeted to EL3 is masked regardless of any indication of Superpriority. PSTATE.ALLINT is set to 0 on taking an exception to EL3. AU When FEAT_NMI is implemented 62 62 62 Reserved, RES0. Otherwise NMI 61 61 0 Non-maskable Interrupt enable. 0b0 This control does not affect interrupt masking behavior. 0b1 This control enables all of the following: The use of the PSTATE.ALLINT interrupt mask. IRQ and FIQ interrupts to have Superpriority as an additional attribute. PSTATE.SP to be used as an interrupt mask. '0' When FEAT_NMI is implemented 61 61 61 Reserved, RES0. Otherwise 60 60 60 Reserved, RES0. TCSO 59 59 0 Tag Checking Store Only. 0b0 This field has no effect on Tag checking. 0b1 Explicit Memory Read Effects generated by instructions executed at EL3 are Tag Unchecked. AU When FEAT_MTE_STORE_ONLY is implemented 59 59 59 Reserved, RES0. Otherwise 58 45 58:45 Reserved, RES0. DSSBS 44 44 0 Default PSTATE.SSBS value on Exception Entry. 0b0 PSTATE.SSBS is set to 0 on an exception to EL3. 0b1 PSTATE.SSBS is set to 1 on an exception to EL3. ID When FEAT_SSBS is implemented 44 44 44 Reserved, RES0. Otherwise ATA 43 43 0 Allocation Tag Access at EL3. Controls use of Memory tagging at EL3. 0b0 Use of Memory tagging is disabled at EL3. 0b1 Use of Memory tagging is enabled at EL3. AU When FEAT_MTE2 is implemented 43 43 43 Reserved, RES0. Otherwise 42 42 42 Reserved, RES0. TCF 41 40 1:0 Tag Check Fault at EL3. Controls the effect of Tag Check Faults due to Loads and Stores at EL3. If FEAT_MTE3 is not implemented, the value 0b11 is reserved. 0b00 Tag Check Faults have no effect on the PE. 0b01 Tag Check Faults cause a synchronous exception. 0b10 Tag Check Faults are asynchronously accumulated. 0b11 Tag Check Faults cause a synchronous exception on reads, and are asynchronously accumulated on writes. When FEAT_MTE_ASYM_FAULT is implemented AU When FEAT_MTE2 is implemented 41 40 41:40 Reserved, RES0. Otherwise 39 38 39:38 Reserved, RES0. ITFSB 37 37 0 When synchronous exceptions are not being generated by Tag Check Faults, this field controls whether on exception entry into EL3, all Tag Check Faults due to instructions executed before exception entry, that are reported asynchronously, are synchronized into TFSRE0_EL1 and TFSR_ELx registers. 0b0 Tag Check Faults are not synchronized on entry to EL3. 0b1 Tag Check Faults are synchronized on entry to EL3. AU When FEAT_MTE_ASYNC is implemented 37 37 37 Reserved, RES0. Otherwise BT 36 36 0 Indicates the Branch Type compatibility of the implicit BTI behavior for the following instructions at EL3: PACIASP. PACIBSP. If FEAT_PAuth_LR is implemented, PACIASPPC. If FEAT_PAuth_LR is implemented, PACIBSPPC. 0b0 When the PE is executing at EL3, when the specified instructions have an implicit BTI behavior, they are compatible with the same BTYPE values as BTI.jc. 0b1 When the PE is executing at EL3, when the specified instructions have an implicit BTI behavior, they are compatible with the same BTYPE values as BTI.c. AU When FEAT_BTI is implemented 36 36 36 Reserved, RES0. Otherwise 35 32 35:32 Reserved, RES0. EnIA 31 31 0 Controls enabling of pointer authentication of instruction addresses, using the APIAKey_EL1 key, in the EL3 translation regime. Possible values of this bit are: This field controls the behavior of the AddPACIA() and AuthIA() pseudocode functions. Specifically, when the field is 1, AddPACIA() returns a copy of a pointer to which a pointer authentication code has been added, and AuthIA() returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP. 0b0 Pointer authentication of instruction addresses, using the APIAKey_EL1 key, is not enabled. 0b1 Pointer authentication of instruction addresses, using the APIAKey_EL1 key, is enabled. AU When FEAT_PAuth is implemented 31 31 31 Reserved, RES0. Otherwise EnIB 30 30 0 Controls enabling of pointer authentication of instruction addresses, using the APIBKey_EL1 key, in the EL3 translation regime. Possible values of this bit are: This field controls the behavior of the AddPACIB() and AuthIB() pseudocode functions. Specifically, when the field is 1, AddPACIB() returns a copy of a pointer to which a pointer authentication code has been added, and AuthIB() returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP. 0b0 Pointer authentication of instruction addresses, using the APIBKey_EL1 key, is not enabled. 0b1 Pointer authentication of instruction addresses, using the APIBKey_EL1 key, is enabled. AU When FEAT_PAuth is implemented 30 30 30 Reserved, RES0. Otherwise 29 28 29:28 Reserved, RES1. EnDA 27 27 0 Controls enabling of pointer authentication of instruction addresses, using the APDAKey_EL1 key, in the EL3 translation regime. This field controls the behavior of the AddPACDA() and AuthDA() pseudocode functions. Specifically, when the field is 1, AddPACDA() returns a copy of a pointer to which a pointer authentication code has been added, and AuthDA() returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP. 0b0 Pointer authentication of data addresses, using the APDAKey_EL1 key, is not enabled. 0b1 Pointer authentication of data addresses, using the APDAKey_EL1 key, is enabled. AU When FEAT_PAuth is implemented 27 27 27 Reserved, RES0. Otherwise 26 26 26 Reserved, RES0. EE 25 25 0 Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime. The EE bit is permitted to be cached in a TLB. 0b0 Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are little-endian. 0b1 Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are big-endian. ID When FEAT_MixedEnd is implemented 25 25 0 Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are big-endian. Reserved, RES1. When FEAT_BigEnd is implemented 25 25 0 Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are little-endian. Reserved, RES0. Otherwise 24 24 24 Reserved, RES0. 23 23 23 Reserved, RES1. EIS 22 22 0 Exception Entry is a context synchronization event. If SCTLR_EL3.EIS is set to 0: Indirect writes to ESR_EL3, FAR_EL3, SPSR_EL3, ELR_EL3 are synchronized on exception entry to EL3, so that a direct read of the register after exception entry sees the indirectly written value caused by the exception entry. Memory transactions, including instruction fetches, from an Exception level always use the translation resources associated with that translation regime. Exception Catch debug events are synchronous debug events. DCPS* and DRPS instructions are context synchronization events. Some exception entries reported are not considered IFBEs per the memory model. The following are not affected by the value of SCTLR_EL3.EIS: Changes to the PSTATE information on entry to EL3. Behavior of accessing the banked copies of the stack pointer using the SP register name for loads, stores and data processing instructions. The memory model requirement for exception entry to generate an Instruction Fetch Barrier Effect for some exception entries. See Basic definitions for the list of exception entries. Exit from Debug state. 0b0 The taking of an exception to EL3 is not a context synchronization event. 0b1 The taking of an exception to EL3 is a context synchronization event. AU When FEAT_ExS is implemented 22 22 22 Reserved, RES1. Otherwise IESB 21 21 0 Implicit Error Synchronization event enable. The value of this field is ignored in Debug state and treated as zero. When FEAT_DoubleFault is implemented, the PE is in Non-debug state, and the Effective value of SCR_EL3.NMEA is 1, this field is ignored and its Effective value is 1. 0b0 Disabled. 0b1 An implicit error synchronization event is added: At each exception taken to EL3. Before the operational pseudocode of each Exception Return instruction executed at EL3. AU When FEAT_IESB is implemented 21 21 21 Reserved, RES0. Otherwise 20 20 20 Reserved, RES0. WXN 19 19 19 Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN. This bit applies only when SCTLR_EL3.M bit is set. The WXN bit is permitted to be cached in a TLB. This field is RES0 if TCR_EL3.PIE is 1. 0b0 This control has no effect on memory access permissions. 0b1 Any region that is writable in the EL3 translation regime is forced to XN for accesses from software executing at EL3. AU 18 18 18 Reserved, RES1. 17 17 17 Reserved, RES0. 16 16 16 Reserved, RES1. 15 14 15:14 Reserved, RES0. EnDB 13 13 0 Controls enabling of pointer authentication of instruction addresses, using the APDBKey_EL1 key, in the EL3 translation regime. This field controls the behavior of the AddPACDB() and AuthDB() pseudocode functions. Specifically, when the field is 1, AddPACDB() returns a copy of a pointer to which a pointer authentication code has been added, and AuthDB() returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP. 0b0 Pointer authentication of data addresses, using the APDBKey_EL1 key, is not enabled. 0b1 Pointer authentication of data addresses, using the APDBKey_EL1 key, is enabled. AU When FEAT_PAuth is implemented 13 13 13 Reserved, RES0. Otherwise I 12 12 12 Instruction access Cacheability control, for accesses at EL3: This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes. 0b0 All instruction access to Normal memory from EL3 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. 0b1 This control has no effect on the Cacheability of instruction access to Normal memory from EL3. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. '0' EOS 11 11 0 Exception Exit is a context synchronization event. If SCTLR_EL3.EOS is set to 0: Memory transactions, including instruction fetches, from an Exception level always use the translation resources associated with that translation regime. Exception Catch debug events are synchronous debug events. DCPS* and DRPS instructions are context synchronization events. The following are not affected by the value of SCTLR_EL3.EOS: The indirect write of the PSTATE and PC values from SPSR_EL3 and ELR_EL3 on exception return is synchronized. If the PE enters Debug state before the first instruction after an Exception return from EL3 to Non-secure state, any pending Halting debug event completes execution. The GIC behavior that allocates interrupts to FIQ or IRQ changes simultaneously with leaving the EL3 Exception level. Behavior of accessing the banked copies of the stack pointer using the SP register name for loads, stores and data processing instructions. Exit from Debug state. 0b0 An exception return from EL3 is not a context synchronization event 0b1 An exception return from EL3 is a context synchronization event AU When FEAT_ExS is implemented 11 11 11 Reserved, RES1. Otherwise 10 7 10:7 Reserved, RES0. nAA 6 6 0 Non-aligned access. This bit controls generation of Alignment faults at EL3 under certain conditions. The following instructions generate an Alignment fault if all bytes being accessed are not within a single naturally aligned 16-byte quantity, for access: LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH, LDLAR, LDLARH. STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH. If FEAT_LRCPC3 is implemented, the post index versions of LDAPR and the pre index versions of STLR. If FEAT_LRCPC3 and Advanced SIMD and floating-point instructions are implemented, LDAPUR (SIMD&FP), LDAP1 (SIMD&FP), STLUR (SIMD&FP), and STL1 (SIMD&FP). If FEAT_LRCPC3 is implemented, the following instructions generate an Alignment fault if all bytes being accessed for a single register are not within a single naturally aligned 16-byte quantity, for access: LDIAPP, STILP. For a load-acquire instruction that does not have acquire semantics as the result of the destination register, or registers, being ZR, it is IMPLEMENTATION SPECIFIC whether this field behaves as 1 or the programmed value. 0b0 Unaligned accesses by the specified instructions generate an Alignment fault. 0b1 Unaligned accesses by the specified instructions do not generate an Alignment fault. AU When FEAT_LSE2 is implemented 6 6 6 Reserved, RES0. Otherwise 5 4 5:4 Reserved, RES1. SA 3 3 3 SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking'. AU C 2 2 2 Cacheability control, for data accesses. This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes. 0b0 All data access to Normal memory from EL3, and all Normal memory accesses to the EL3 translation tables, are Non-cacheable for all levels of data and unified cache. 0b1 This control has no effect on the Cacheability of: Data access to Normal memory from EL3. Normal memory accesses to the EL3 translation tables. '0' A 1 1 1 Alignment check enable. This is the enable bit for Alignment fault checking at EL3. 0b0 Alignment fault checking is disabled when executing at EL3. Alignment checks on some instructions are not disabled by this control. For more information, see 'Alignment of data accesses'. 0b1 Alignment fault checking is enabled when executing at EL3. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. AU M 0 0 0 MMU enable for EL3 stage 1 address translation. Possible values of this bit are: 0b0 EL3 stage 1 address translation disabled. See the SCTLR_EL3.I field for the behavior of instruction accesses to Normal memory. 0b1 EL3 stage 1 address translation enabled. '0' MRS <Xt>, SCTLR_EL3 if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = SCTLR_EL3(); end; MSR SCTLR_EL3, <Xt> if !(HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().SCTLR_EL3 == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else SCTLR_EL3() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel