SCTLRMASK_EL1 System Control Masking Register (EL1) when FEAT_SRMASK is implemented and FEAT_AA64 is implemented Mask register to prevent updates of fields in SCTLR_EL1 on writes to SCTLR_EL1 or SCTLRALIAS_EL1. Other SCTLRMASK_EL1 is a 64-bit register. TIDCP 63 63 0 Mask bit for TIDCP. 0b0 SCTLR_EL1.TIDCP is writable. 0b1 SCTLR_EL1.TIDCP is not writable. '0' AU When FEAT_TIDCP1 is implemented 63 63 63 Reserved, RES0. Otherwise SPINTMASK 62 62 0 Mask bit for SPINTMASK. 0b0 SCTLR_EL1.SPINTMASK is writable. 0b1 SCTLR_EL1.SPINTMASK is not writable. '0' AU When FEAT_NMI is implemented 62 62 62 Reserved, RES0. Otherwise NMI 61 61 0 Mask bit for NMI. 0b0 SCTLR_EL1.NMI is writable. 0b1 SCTLR_EL1.NMI is not writable. '0' AU When FEAT_NMI is implemented 61 61 61 Reserved, RES0. Otherwise EnTP2 60 60 0 Mask bit for EnTP2. 0b0 SCTLR_EL1.EnTP2 is writable. 0b1 SCTLR_EL1.EnTP2 is not writable. '0' AU When FEAT_SME is implemented 60 60 60 Reserved, RES0. Otherwise TCSO 59 59 0 Mask bit for TCSO. 0b0 SCTLR_EL1.TCSO is writable. 0b1 SCTLR_EL1.TCSO is not writable. '0' AU When FEAT_MTE_STORE_ONLY is implemented 59 59 59 Reserved, RES0. Otherwise TCSO0 58 58 0 Mask bit for TCSO0. 0b0 SCTLR_EL1.TCSO0 is writable. 0b1 SCTLR_EL1.TCSO0 is not writable. '0' AU When FEAT_MTE_STORE_ONLY is implemented 58 58 58 Reserved, RES0. Otherwise EPAN 57 57 0 Mask bit for EPAN. 0b0 SCTLR_EL1.EPAN is writable. 0b1 SCTLR_EL1.EPAN is not writable. '0' AU When FEAT_PAN3 is implemented 57 57 57 Reserved, RES0. Otherwise EnALS 56 56 0 Mask bit for EnALS. 0b0 SCTLR_EL1.EnALS is writable. 0b1 SCTLR_EL1.EnALS is not writable. '0' AU When FEAT_LS64 is implemented 56 56 56 Reserved, RES0. Otherwise EnAS0 55 55 0 Mask bit for EnAS0. 0b0 SCTLR_EL1.EnAS0 is writable. 0b1 SCTLR_EL1.EnAS0 is not writable. '0' AU When FEAT_LS64_ACCDATA is implemented 55 55 55 Reserved, RES0. Otherwise EnASR 54 54 0 Mask bit for EnASR. 0b0 SCTLR_EL1.EnASR is writable. 0b1 SCTLR_EL1.EnASR is not writable. '0' AU When FEAT_LS64_V is implemented 54 54 54 Reserved, RES0. Otherwise 53 47 53:47 Reserved, RES0. TWEDEL 46 46 0 Mask bit for TWEDEL. 0b0 SCTLR_EL1.TWEDEL is writable. 0b1 SCTLR_EL1.TWEDEL is not writable. '0' AU When FEAT_TWED is implemented 46 46 46 Reserved, RES0. Otherwise TWEDEn 45 45 0 Mask bit for TWEDEn. 0b0 SCTLR_EL1.TWEDEn is writable. 0b1 SCTLR_EL1.TWEDEn is not writable. '0' AU When FEAT_TWED is implemented 45 45 45 Reserved, RES0. Otherwise DSSBS 44 44 0 Mask bit for DSSBS. 0b0 SCTLR_EL1.DSSBS is writable. 0b1 SCTLR_EL1.DSSBS is not writable. '0' AU When FEAT_SSBS is implemented 44 44 44 Reserved, RES0. Otherwise ATA 43 43 0 Mask bit for ATA. 0b0 SCTLR_EL1.ATA is writable. 0b1 SCTLR_EL1.ATA is not writable. '0' AU When FEAT_MTE2 is implemented 43 43 43 Reserved, RES0. Otherwise ATA0 42 42 0 Mask bit for ATA0. 0b0 SCTLR_EL1.ATA0 is writable. 0b1 SCTLR_EL1.ATA0 is not writable. '0' AU When FEAT_MTE2 is implemented 42 42 42 Reserved, RES0. Otherwise 41 41 41 Reserved, RES0. TCF 40 40 0 Mask bit for TCF. 0b0 SCTLR_EL1.TCF is writable. 0b1 SCTLR_EL1.TCF is not writable. '0' AU When FEAT_MTE2 is implemented 40 40 40 Reserved, RES0. Otherwise 39 39 39 Reserved, RES0. TCF0 38 38 0 Mask bit for TCF0. 0b0 SCTLR_EL1.TCF0 is writable. 0b1 SCTLR_EL1.TCF0 is not writable. '0' AU When FEAT_MTE2 is implemented 38 38 38 Reserved, RES0. Otherwise ITFSB 37 37 0 Mask bit for ITFSB. 0b0 SCTLR_EL1.ITFSB is writable. 0b1 SCTLR_EL1.ITFSB is not writable. '0' AU When FEAT_MTE_ASYNC is implemented 37 37 37 Reserved, RES0. Otherwise BT1 36 36 0 Mask bit for BT1. 0b0 SCTLR_EL1.BT1 is writable. 0b1 SCTLR_EL1.BT1 is not writable. '0' AU When FEAT_BTI is implemented 36 36 36 Reserved, RES0. Otherwise BT0 35 35 0 Mask bit for BT0. 0b0 SCTLR_EL1.BT0 is writable. 0b1 SCTLR_EL1.BT0 is not writable. '0' AU When FEAT_BTI is implemented 35 35 35 Reserved, RES0. Otherwise EnFPM 34 34 0 Mask bit for EnFPM. 0b0 SCTLR_EL1.EnFPM is writable. 0b1 SCTLR_EL1.EnFPM is not writable. '0' AU When FEAT_FPMR is implemented 34 34 34 Reserved, RES0. Otherwise MSCEn 33 33 0 Mask bit for MSCEn. 0b0 SCTLR_EL1.MSCEn is writable. 0b1 SCTLR_EL1.MSCEn is not writable. '0' AU When FEAT_MOPS is implemented 33 33 33 Reserved, RES0. Otherwise CMOW 32 32 0 Mask bit for CMOW. 0b0 SCTLR_EL1.CMOW is writable. 0b1 SCTLR_EL1.CMOW is not writable. '0' AU When FEAT_CMOW is implemented 32 32 32 Reserved, RES0. Otherwise EnIA 31 31 0 Mask bit for EnIA. 0b0 SCTLR_EL1.EnIA is writable. 0b1 SCTLR_EL1.EnIA is not writable. '0' AU When FEAT_PAuth is implemented 31 31 31 Reserved, RES0. Otherwise EnIB 30 30 0 Mask bit for EnIB. 0b0 SCTLR_EL1.EnIB is writable. 0b1 SCTLR_EL1.EnIB is not writable. '0' AU When FEAT_PAuth is implemented 30 30 30 Reserved, RES0. Otherwise LSMAOE 29 29 0 Mask bit for LSMAOE. 0b0 SCTLR_EL1.LSMAOE is writable. 0b1 SCTLR_EL1.LSMAOE is not writable. '0' AU When FEAT_LSMAOC is implemented 29 29 29 Reserved, RES0. Otherwise nTLSMD 28 28 0 Mask bit for nTLSMD. 0b0 SCTLR_EL1.nTLSMD is writable. 0b1 SCTLR_EL1.nTLSMD is not writable. '0' AU When FEAT_LSMAOC is implemented 28 28 28 Reserved, RES0. Otherwise EnDA 27 27 0 Mask bit for EnDA. 0b0 SCTLR_EL1.EnDA is writable. 0b1 SCTLR_EL1.EnDA is not writable. '0' AU When FEAT_PAuth is implemented 27 27 27 Reserved, RES0. Otherwise UCI 26 26 26 Mask bit for UCI. 0b0 SCTLR_EL1.UCI is writable. 0b1 SCTLR_EL1.UCI is not writable. '0' AU EE 25 25 0 Mask bit for EE. 0b0 SCTLR_EL1.EE is writable. 0b1 SCTLR_EL1.EE is not writable. '0' AU When FEAT_MixedEnd is implemented 25 25 25 Reserved, RES0. Otherwise E0E 24 24 0 Mask bit for E0E. 0b0 SCTLR_EL1.E0E is writable. 0b1 SCTLR_EL1.E0E is not writable. '0' AU When FEAT_MixedEndEL0 is implemented 24 24 24 Reserved, RES0. Otherwise SPAN 23 23 0 Mask bit for SPAN. 0b0 SCTLR_EL1.SPAN is writable. 0b1 SCTLR_EL1.SPAN is not writable. '0' AU When FEAT_PAN is implemented 23 23 23 Reserved, RES0. Otherwise EIS 22 22 0 Mask bit for EIS. 0b0 SCTLR_EL1.EIS is writable. 0b1 SCTLR_EL1.EIS is not writable. '0' AU When FEAT_ExS is implemented 22 22 22 Reserved, RES0. Otherwise IESB 21 21 0 Mask bit for IESB. 0b0 SCTLR_EL1.IESB is writable. 0b1 SCTLR_EL1.IESB is not writable. '0' AU When FEAT_IESB is implemented 21 21 21 Reserved, RES0. Otherwise TSCXT 20 20 0 Mask bit for TSCXT. 0b0 SCTLR_EL1.TSCXT is writable. 0b1 SCTLR_EL1.TSCXT is not writable. '0' AU When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented 20 20 20 Reserved, RES0. Otherwise WXN 19 19 19 Mask bit for WXN. 0b0 SCTLR_EL1.WXN is writable. 0b1 SCTLR_EL1.WXN is not writable. '0' AU nTWE 18 18 18 Mask bit for nTWE. 0b0 SCTLR_EL1.nTWE is writable. 0b1 SCTLR_EL1.nTWE is not writable. '0' AU 17 17 17 Reserved, RES0. nTWI 16 16 16 Mask bit for nTWI. 0b0 SCTLR_EL1.nTWI is writable. 0b1 SCTLR_EL1.nTWI is not writable. '0' AU UCT 15 15 15 Mask bit for UCT. 0b0 SCTLR_EL1.UCT is writable. 0b1 SCTLR_EL1.UCT is not writable. '0' AU DZE 14 14 14 Mask bit for DZE. 0b0 SCTLR_EL1.DZE is writable. 0b1 SCTLR_EL1.DZE is not writable. '0' AU EnDB 13 13 0 Mask bit for EnDB. 0b0 SCTLR_EL1.EnDB is writable. 0b1 SCTLR_EL1.EnDB is not writable. '0' AU When FEAT_PAuth is implemented 13 13 13 Reserved, RES0. Otherwise I 12 12 12 Mask bit for I. 0b0 SCTLR_EL1.I is writable. 0b1 SCTLR_EL1.I is not writable. '0' AU EOS 11 11 0 Mask bit for EOS. 0b0 SCTLR_EL1.EOS is writable. 0b1 SCTLR_EL1.EOS is not writable. '0' AU When FEAT_ExS is implemented 11 11 11 Reserved, RES0. Otherwise EnRCTX 10 10 0 Mask bit for EnRCTX. 0b0 SCTLR_EL1.EnRCTX is writable. 0b1 SCTLR_EL1.EnRCTX is not writable. '0' AU When FEAT_SPECRES is implemented 10 10 10 Reserved, RES0. Otherwise UMA 9 9 9 Mask bit for UMA. 0b0 SCTLR_EL1.UMA is writable. 0b1 SCTLR_EL1.UMA is not writable. '0' AU SED 8 8 0 Mask bit for SED. 0b0 SCTLR_EL1.SED is writable. 0b1 SCTLR_EL1.SED is not writable. '0' AU When FEAT_AA32EL0 is implemented 8 8 8 Reserved, RES0. Otherwise ITD 7 7 0 Mask bit for ITD. 0b0 SCTLR_EL1.ITD is writable. 0b1 SCTLR_EL1.ITD is not writable. '0' AU When FEAT_AA32EL0 is implemented 7 7 7 Reserved, RES0. Otherwise nAA 6 6 0 Mask bit for nAA. 0b0 SCTLR_EL1.nAA is writable. 0b1 SCTLR_EL1.nAA is not writable. '0' AU When FEAT_LSE2 6 6 6 Reserved, RES0. Otherwise CP15BEN 5 5 0 Mask bit for CP15BEN. 0b0 SCTLR_EL1.CP15BEN is writable. 0b1 SCTLR_EL1.CP15BEN is not writable. '0' AU When FEAT_AA32EL0 is implemented 5 5 5 Reserved, RES0. Otherwise SA0 4 4 4 Mask bit for SA0. 0b0 SCTLR_EL1.SA0 is writable. 0b1 SCTLR_EL1.SA0 is not writable. '0' AU SA 3 3 3 Mask bit for SA. 0b0 SCTLR_EL1.SA is writable. 0b1 SCTLR_EL1.SA is not writable. '0' AU C 2 2 2 Mask bit for C. 0b0 SCTLR_EL1.C is writable. 0b1 SCTLR_EL1.C is not writable. '0' AU A 1 1 1 Mask bit for A. 0b0 SCTLR_EL1.A is writable. 0b1 SCTLR_EL1.A is not writable. '0' AU M 0 0 0 Mask bit for M. 0b0 SCTLR_EL1.M is writable. 0b1 SCTLR_EL1.M is not writable. '0' AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SCTLRMASK_EL1 or SCTLRMASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, SCTLRMASK_EL1 if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nSCTLRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x318); else X{64}(t) = SCTLRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = SCTLRMASK_EL2(); else X{64}(t) = SCTLRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SCTLRMASK_EL1(); end; MSR SCTLRMASK_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nSCTLRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x318) = X{64}(t); elsif !IsZero(SCTLRMASK_EL1()) then Undefined(); else SCTLRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(SCTLRMASK_EL2()) then Undefined(); else SCTLRMASK_EL2() = X{64}(t); end; else SCTLRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SCTLRMASK_EL1() = X{64}(t); end; MRS <Xt>, SCTLRMASK_EL12 When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x318); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SCTLRMASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = SCTLRMASK_EL1(); else Undefined(); end; end; MSR SCTLRMASK_EL12, <Xt> When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x318) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SCTLRMASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SCTLRMASK_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel