SMIDR_EL1 Streaming Mode Identification Register when FEAT_SME is implemented and FEAT_AA64 is implemented Provides additional identification mechanisms for scheduling purposes, for a PE that supports Streaming SVE mode. Identification Registers SMIDR_EL1 is a 64-bit register. 63 60 63:60 Reserved, RES0. NSMC 59 56 59:56 If SMIDR_EL1.{SH,Affinity} indicates that the implementation of Streaming SVE mode is shared, then this field identifies the number of SMCUs, minus 1, associated with the concatenated SMIDR_EL1.{Affinity2,Affinity} 32-bit value. If SMIDR_EL1.{SH,Affinity} indicates that the implementation of Streaming SVE mode is not shared, then this field is zero and should be ignored by software. 0b0000 The implementation of Streaming SVE mode associated with this PE is not shared or is a single SMCU. 0b0001..0b1110 The number of SMCUs in the group of SMCUs providing the implementation of Streaming SVE mode for this PE, minus 1. 0b1111 Reserved. RO HIP 55 52 3:0 Highest Implemented Priority. If Streaming SVE mode execution priority is supported, this field indicates the range of priority levels implemented by the PE, and the Highest Implemented Priority value. 0b0000 All streaming execution priorities from 0 to 15 are implemented. The Highest Implemented Priority value is 15. 0b0001..0b1111 All streaming execution priorities less than or equal to this value are implemented. The Highest Implemented Priority value is the value of this field. RO When FEAT_SME2p2 is implemented and SMIDR_EL1.SMPS == '1' 55 52 55:52 Reserved, RES0. Otherwise Affinity2 51 32 51:32 The most significant 20 bits of the SMCU affinity for this PE, to be used in conjunction with SMIDR_EL1.Affinity. This field has an IMPLEMENTATION DEFINED value. RO Implementer 31 24 31:24 The Implementer code. This field must hold an implementer code that has been assigned by Arm. Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used. It is not required that this value is the same as the value of MIDR_EL1.Implementer. 0x00 Reserved for software use. 0x41 Arm Limited. 0x42 Broadcom Corporation. 0x43 Cavium Inc. 0x44 Digital Equipment Corporation. 0x46 Fujitsu Ltd. 0x49 Infineon Technologies AG. 0x4D Motorola or Freescale Semiconductor Inc. 0x4E NVIDIA Corporation. 0x50 Applied Micro Circuits Corporation. 0x51 Qualcomm Inc. 0x56 Marvell International Ltd. 0x69 Intel Corporation. 0xC0 Ampere Computing. RO Revision 23 16 23:16 Revision number for the Streaming Mode Compute Unit (SMCU). This field has an IMPLEMENTATION DEFINED value. RO SMPS 15 15 15 Indicates support for Streaming SVE mode execution priority. 0b0 Priority control not supported. 0b1 Priority control supported. RO SH 14 13 14:13 Indicates whether the implementation of Streaming SVE mode in this PE is shared with other PEs. 0b00 Refer to SMIDR_EL1.Affinity. 0b01 Reserved. 0b10 The implementation of Streaming SVE mode is not shared with other PEs. 0b11 The implementation of Streaming SVE mode is shared with other PEs. RO 12 12 12 Reserved, RES0. Affinity 11 0 11:0 The least significant 12 bits of the SMCU affinity for this PE. If the implementation of Streaming SVE mode is shared, then the concatenated SMIDR_EL1.{Affinity2,Affinity} 32-bit value identifies which shared SMCUs are associated with this PE. Every PE that shares the same SMCUs has the same 32-bit affinity value. The 32-bit affinity value is unique within the system as a whole. The SMIDR_EL1.SH field indicates whether the implementation of Streaming SVE mode is shared with other PEs. However, if SMIDR_EL1.SH is zero, then SMIDR_EL1.Affinity is used to indicate whether the implementation of Streaming SVE is shared, as follows: If SMIDR_EL1.Affinity is zero, then the implementation of Streaming SVE mode is not shared with other PEs. If SMIDR_EL1.Affinity is not zero, then the implementation of Streaming SVE mode is shared with other PEs. This field has an IMPLEMENTATION DEFINED value. RO MRS <Xt>, SMIDR_EL1 if !(IsFeatureImplemented(FEAT_SME) && IsFeatureImplemented(FEAT_AA64)) then UnimplementedIDRegister(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TID1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = SMIDR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = SMIDR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = SMIDR_EL1(); end; 2026-03-26 20:27:25 2026-03_rel