SMPRI_EL1 Streaming Mode Priority Register when FEAT_SME is implemented and FEAT_AA64 is implemented Configures the streaming execution priority for instructions executed on a shared Streaming Mode Compute Unit (SMCU) when the PE is in Streaming SVE mode at any Exception level. Other When SMIDR_EL1.SMPS is '0', this register is RES0. SMPRI_EL1 is a 64-bit register. 63 4 63:4 Reserved, RES0. Priority 3 0 3:0 Streaming execution priority value. Either this value is used directly, or it is mapped into an effective priority value using SMPRIMAP_EL2. This value is used directly when any of the following are true: The current Exception level is EL3 or EL2. The current Exception level is EL1 or EL0, if EL2 is implemented and enabled in the current Security state and HCRX_EL2.SMPME is '0'. The current Exception level is EL1 or EL0, if EL2 is either not implemented or not enabled in the current Security state. The precise meaning and behavior of each streaming execution priority value is IMPLEMENTATION DEFINED. In an implementation that shares execution resources between PEs, higher priority values are allocated more processing resource than other PEs configured with lower priority values in the same Priority domain. If FEAT_SME2p2 is implemented, and this field is greater than the Highest Implemented Priority value indicated by SMIDR_EL1.HIP, then the PE uses the Highest Implemented Priority value as the priority. AU MRS <Xt>, SMPRI_EL1 if !(IsFeatureImplemented(FEAT_SME) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().ESM == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().nSMPRI_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().ESM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SMPRI_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().ESM == '0' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().ESM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SMPRI_EL1(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().ESM == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = SMPRI_EL1(); end; end; MSR SMPRI_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SME) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().ESM == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().nSMPRI_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().ESM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SMPRI_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().ESM == '0' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().ESM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SMPRI_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().ESM == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else SMPRI_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel