SMPRIMAP_EL2 Streaming Mode Priority Mapping Register when FEAT_SME is implemented and FEAT_AA64 is implemented Maps the value in SMPRI_EL1 to a streaming execution priority value for instructions executed at EL1 and EL0 in the same Security states as EL2. Other When SMIDR_EL1.SMPS is '0', this register is RES0. If EL2 is not implemented, this register is RES0 from EL3. SMPRIMAP_EL2 is a 64-bit register. When all of the following are true, the value in SMPRI_EL1 is mapped to a streaming execution priority using this register: The current Exception level is EL1 or EL0. EL2 is implemented and enabled in the current Security state. HCRX_EL2.SMPME is '1'. Otherwise, SMPRI_EL1 holds the streaming execution priority value. P15 63 60 63:60 Priority Mapping Entry 15. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '15'. This value is the highest streaming execution priority. AU P14 59 56 59:56 Priority Mapping Entry 14. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '14'. AU P13 55 52 55:52 Priority Mapping Entry 13. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '13'. AU P12 51 48 51:48 Priority Mapping Entry 12. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '12'. AU P11 47 44 47:44 Priority Mapping Entry 11. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '11'. AU P10 43 40 43:40 Priority Mapping Entry 10. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '10'. AU P9 39 36 39:36 Priority Mapping Entry 9. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '9'. AU P8 35 32 35:32 Priority Mapping Entry 8. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '8'. AU P7 31 28 31:28 Priority Mapping Entry 7. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '7'. AU P6 27 24 27:24 Priority Mapping Entry 6. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '6'. AU P5 23 20 23:20 Priority Mapping Entry 5. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '5'. AU P4 19 16 19:16 Priority Mapping Entry 4. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '4'. AU P3 15 12 15:12 Priority Mapping Entry 3. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '3'. AU P2 11 8 11:8 Priority Mapping Entry 2. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '2'. AU P1 7 4 7:4 Priority Mapping Entry 1. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '1'. AU P0 3 0 3:0 Priority Mapping Entry 0. This entry is used when priority mapping is supported and enabled, and the SMPRI_EL1.Priority value is '0'. This value is the lowest streaming execution priority. AU MRS <Xt>, SMPRIMAP_EL2 if !(IsFeatureImplemented(FEAT_SME) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1F8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().ESM == '0' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().ESM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SMPRIMAP_EL2(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().ESM == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = SMPRIMAP_EL2(); end; end; MSR SMPRIMAP_EL2, <Xt> if !(IsFeatureImplemented(FEAT_SME) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1F8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().ESM == '0' then Undefined(); elsif HaveEL(EL3) && CPTR_EL3().ESM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SMPRIMAP_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().ESM == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else SMPRIMAP_EL2() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel