SPMCFGR_EL1 System Performance Monitors Configuration Register when FEAT_SPMU is implemented and FEAT_AA64 is implemented Describes the capabilities of System PMU <s>. Unknown SPMCFGR_EL1 is a 64-bit register. 63 32 63:32 Reserved, RES0. NCG 31 28 31:28 Counter Groups. Defines the number of counter groups implemented by System PMU <s>, minus one. If this field is zero, then one counter group is implemented and SPMCGCR<n>_EL1 read-as-zero. Otherwise, for each counter group <m>, SPMCGCR<m DIV 8>_EL1.N<m MOD 8> defines the number of counters in the group. Locating the first counter in each group depends on the number of implemented groups. Each counter group starts with counter: SPMEVTYPER<m×32>_EL0, meaning there are at most 32 counters per group, if there are 2 counter groups. SPMEVTYPER<m×16>_EL0, meaning there are at most 16 counters per group, if there are 3 or 4 counter groups. SPMEVTYPER<m×8>_EL0, meaning there are at most 8 counters per group, if there are between 5 and 8 counter groups. SPMEVTYPER<m×4>_EL0, meaning there are at most 4 counters per group, if there are more than 8 counter groups. This field has an IMPLEMENTATION DEFINED value. RO 27 25 27:25 Reserved, RES0. HDBG 24 24 24 Halt-on-debug supported. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO TRO 23 23 23 Trace output supported. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO SS 22 22 22 Snapshot supported. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO FZO 21 21 21 Freeze-on-overflow supported. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO MSI 20 20 20 Message-signaled interrupts supported. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO 19 19 19 Reserved, RAO. 18 18 18 Reserved, RES0. NA 17 17 17 No write access when running. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO EX 16 16 16 Export supported. For more information on this field, see 'CoreSight PMU Architecture'. This field has an IMPLEMENTATION DEFINED value. RO 15 14 15:14 Reserved, RAZ. SIZE 13 8 13:8 Counter size. The size of the largest counter implemented by System PMU <s>. All other values are reserved. Not all counters must be this size. For example, a System PMU might include a mix of 32-bit and 64-bit counters. 0b000111 8-bit counters. 0b001001 10-bit counters. 0b001011 12-bit counters. 0b001111 16-bit counters. 0b010011 20-bit counters. 0b010111 24-bit counters. 0b011111 32-bit counters. 0b100011 36-bit counters. 0b100111 40-bit counters. 0b101011 44-bit counters. 0b101111 48-bit counters. 0b110011 52-bit counters. 0b110111 56-bit counters. 0b111111 64-bit counters. N 7 0 7:0 Number of event counters implemented by System PMU <s>, minus 1. All other values are reserved. 0x00..0x3F Number of event counters implemented by System PMU <s>, minus 1. To access SPMCFGR_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s. SPMCFGR_EL1 reads-as-zero if System PMU <s> is not implemented. MRS <Xt>, SPMCFGR_EL1 if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMID == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMCFGR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMCFGR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)); end; elsif PSTATE.EL == EL3 then X{64}(t) = SPMCFGR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)); end; 2026-03-26 20:27:25 2026-03_rel