<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>SPMCGCR&lt;n&gt;_EL1</reg_short_name>
        
        <reg_long_name>System PMU Counter Group Configuration Registers</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_SPMU is implemented and FEAT_AA64 is implemented</reg_condition>
          <reg_array>
              <reg_array_start>0</reg_array_start>
              <reg_array_end>1</reg_array_end>
         </reg_array>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Describes the configuration of counter groups in System PMU &lt;s&gt;.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Unknown</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>SPMCGCR&lt;n&gt;_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>N&lt;m&gt;</field_name>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before"><para>Number of counters in counter group 8n+m.</para>
<para>The maximum size of each counter group depends on the number of implemented groups and the largest implemented counter size. For more information, see <register_link state="AArch64" id="AArch64-spmcfgr_el1.xml">SPMCFGR_EL1</register_link>.NCG.</para></field_description>
    <field_array_indexes index_variable="m" element_size="8" range_specifier="8m+7:8m">
      <field_array_index>
        <field_array_start>7</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" label="N7" msb="63" lsb="56"/>
  <fieldat id="fieldset_0-63_0" label="N6" msb="55" lsb="48"/>
  <fieldat id="fieldset_0-63_0" label="N5" msb="47" lsb="40"/>
  <fieldat id="fieldset_0-63_0" label="N4" msb="39" lsb="32"/>
  <fieldat id="fieldset_0-63_0" label="N3" msb="31" lsb="24"/>
  <fieldat id="fieldset_0-63_0" label="N2" msb="23" lsb="16"/>
  <fieldat id="fieldset_0-63_0" label="N1" msb="15" lsb="8"/>
  <fieldat id="fieldset_0-63_0" label="N0" msb="7" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>
        <reg_variables>
              <reg_variable variable="n" max="1"/>
        </reg_variables>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>To access SPMCGCR&lt;n&gt;_EL1 for System PMU &lt;s&gt;, set <register_link state="AArch64" id="AArch64-spmselr_el0.xml">SPMSELR_EL0</register_link>.SYSPMUSEL to s.</para>

      </access_permission_text>
      <access_permission_text>
        <para>SPMCGCR&lt;n&gt;_EL1 reads-as-zero if any of the following are true:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>System PMU &lt;s&gt; implements one counter group (<register_link state="AArch64" id="AArch64-spmcfgr_el1.xml">SPMCFGR_EL1</register_link>.NCG is zero).</content>
</listitem><listitem><content>System PMU &lt;s&gt; is not implemented.</content>
</listitem></list>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS SPMCGCR&lt;m&gt;_EL1" type="SystemAccessor">
            <encoding>
                
                <acc_array var="m">
                    <acc_array_range>0-1</acc_array_range>
                </acc_array>
            <access_instruction>MRS &lt;Xt&gt;, SPMCGCR&lt;m&gt;_EL1</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1001"/>
                
                <enc n="CRm" v="0b1101"/>
                
                <enc n="op2" v="0b00:m[0]"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
let m:integer = UInt(op2[0]);

if !(IsFeatureImplemented(FEAT_SPMU) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMID == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().EnSPM == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMCGCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL), m);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMCGCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL), m);
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = SPMCGCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL), m);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>