<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>SPMCNTENCLR_EL0</reg_short_name>
        
        <reg_long_name>System Performance Monitors Count Enable Clear Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_SPMU is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Disable event counters in System PMU &lt;s&gt;.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Unknown</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>SPMCNTENCLR_EL0 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>P&lt;m&gt;</field_name>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before">
      <para>Event counter &lt;m&gt; disable.</para>
    </field_description>
    <field_array_indexes index_variable="m" element_size="1" range_specifier="m">
      <field_array_index>
        <field_array_start>63</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Event counter &lt;m&gt; in System PMU &lt;s&gt; is disabled.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Event counter &lt;m&gt; in System PMU &lt;s&gt; is enabled.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="System PMU">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level>When event counter &lt;m&gt; is not implemented by System PMU &lt;s&gt;</field_access_level>
        <field_access_type>RAZ/WI</field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>W1C</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" label="P63" msb="63" lsb="63"/>
  <fieldat id="fieldset_0-63_0" label="P62" msb="62" lsb="62"/>
  <fieldat id="fieldset_0-63_0" label="P61" msb="61" lsb="61"/>
  <fieldat id="fieldset_0-63_0" label="P60" msb="60" lsb="60"/>
  <fieldat id="fieldset_0-63_0" label="P59" msb="59" lsb="59"/>
  <fieldat id="fieldset_0-63_0" label="P58" msb="58" lsb="58"/>
  <fieldat id="fieldset_0-63_0" label="P57" msb="57" lsb="57"/>
  <fieldat id="fieldset_0-63_0" label="P56" msb="56" lsb="56"/>
  <fieldat id="fieldset_0-63_0" label="P55" msb="55" lsb="55"/>
  <fieldat id="fieldset_0-63_0" label="P54" msb="54" lsb="54"/>
  <fieldat id="fieldset_0-63_0" label="P53" msb="53" lsb="53"/>
  <fieldat id="fieldset_0-63_0" label="P52" msb="52" lsb="52"/>
  <fieldat id="fieldset_0-63_0" label="P51" msb="51" lsb="51"/>
  <fieldat id="fieldset_0-63_0" label="P50" msb="50" lsb="50"/>
  <fieldat id="fieldset_0-63_0" label="P49" msb="49" lsb="49"/>
  <fieldat id="fieldset_0-63_0" label="P48" msb="48" lsb="48"/>
  <fieldat id="fieldset_0-63_0" label="P47" msb="47" lsb="47"/>
  <fieldat id="fieldset_0-63_0" label="P46" msb="46" lsb="46"/>
  <fieldat id="fieldset_0-63_0" label="P45" msb="45" lsb="45"/>
  <fieldat id="fieldset_0-63_0" label="P44" msb="44" lsb="44"/>
  <fieldat id="fieldset_0-63_0" label="P43" msb="43" lsb="43"/>
  <fieldat id="fieldset_0-63_0" label="P42" msb="42" lsb="42"/>
  <fieldat id="fieldset_0-63_0" label="P41" msb="41" lsb="41"/>
  <fieldat id="fieldset_0-63_0" label="P40" msb="40" lsb="40"/>
  <fieldat id="fieldset_0-63_0" label="P39" msb="39" lsb="39"/>
  <fieldat id="fieldset_0-63_0" label="P38" msb="38" lsb="38"/>
  <fieldat id="fieldset_0-63_0" label="P37" msb="37" lsb="37"/>
  <fieldat id="fieldset_0-63_0" label="P36" msb="36" lsb="36"/>
  <fieldat id="fieldset_0-63_0" label="P35" msb="35" lsb="35"/>
  <fieldat id="fieldset_0-63_0" label="P34" msb="34" lsb="34"/>
  <fieldat id="fieldset_0-63_0" label="P33" msb="33" lsb="33"/>
  <fieldat id="fieldset_0-63_0" label="P32" msb="32" lsb="32"/>
  <fieldat id="fieldset_0-63_0" label="P31" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-63_0" label="P30" msb="30" lsb="30"/>
  <fieldat id="fieldset_0-63_0" label="P29" msb="29" lsb="29"/>
  <fieldat id="fieldset_0-63_0" label="P28" msb="28" lsb="28"/>
  <fieldat id="fieldset_0-63_0" label="P27" msb="27" lsb="27"/>
  <fieldat id="fieldset_0-63_0" label="P26" msb="26" lsb="26"/>
  <fieldat id="fieldset_0-63_0" label="P25" msb="25" lsb="25"/>
  <fieldat id="fieldset_0-63_0" label="P24" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-63_0" label="P23" msb="23" lsb="23"/>
  <fieldat id="fieldset_0-63_0" label="P22" msb="22" lsb="22"/>
  <fieldat id="fieldset_0-63_0" label="P21" msb="21" lsb="21"/>
  <fieldat id="fieldset_0-63_0" label="P20" msb="20" lsb="20"/>
  <fieldat id="fieldset_0-63_0" label="P19" msb="19" lsb="19"/>
  <fieldat id="fieldset_0-63_0" label="P18" msb="18" lsb="18"/>
  <fieldat id="fieldset_0-63_0" label="P17" msb="17" lsb="17"/>
  <fieldat id="fieldset_0-63_0" label="P16" msb="16" lsb="16"/>
  <fieldat id="fieldset_0-63_0" label="P15" msb="15" lsb="15"/>
  <fieldat id="fieldset_0-63_0" label="P14" msb="14" lsb="14"/>
  <fieldat id="fieldset_0-63_0" label="P13" msb="13" lsb="13"/>
  <fieldat id="fieldset_0-63_0" label="P12" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-63_0" label="P11" msb="11" lsb="11"/>
  <fieldat id="fieldset_0-63_0" label="P10" msb="10" lsb="10"/>
  <fieldat id="fieldset_0-63_0" label="P9" msb="9" lsb="9"/>
  <fieldat id="fieldset_0-63_0" label="P8" msb="8" lsb="8"/>
  <fieldat id="fieldset_0-63_0" label="P7" msb="7" lsb="7"/>
  <fieldat id="fieldset_0-63_0" label="P6" msb="6" lsb="6"/>
  <fieldat id="fieldset_0-63_0" label="P5" msb="5" lsb="5"/>
  <fieldat id="fieldset_0-63_0" label="P4" msb="4" lsb="4"/>
  <fieldat id="fieldset_0-63_0" label="P3" msb="3" lsb="3"/>
  <fieldat id="fieldset_0-63_0" label="P2" msb="2" lsb="2"/>
  <fieldat id="fieldset_0-63_0" label="P1" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-63_0" label="P0" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>To access SPMCNTENCLR_EL0 for System PMU &lt;s&gt;, set <register_link state="AArch64" id="AArch64-spmselr_el0.xml">SPMSELR_EL0</register_link>.SYSPMUSEL to s.</para>

      </access_permission_text>
      <access_permission_text>
        <para>SPMCNTENCLR_EL0 reads-as-zero and ignores writes if System PMU &lt;s&gt; is not implemented.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS SPMCNTENCLR_EL0" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, SPMCNTENCLR_EL0</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b1001"/>
                
                <enc n="CRm" v="0b1100"/>
                
                <enc n="op2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_SPMU) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif MDSCR_EL1().EnSPM == '0' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif !ELIsInHost(EL0) &amp;&amp; SPMACCESSR_EL1()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; !ELIsInHost(EL0) &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMCNTEN == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().EnSPM == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL));
    end;
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMCNTEN == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().EnSPM == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL));
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL));
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL));
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister SPMCNTENCLR_EL0" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR SPMCNTENCLR_EL0, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b1001"/>
                
                <enc n="CRm" v="0b1100"/>
                
                <enc n="op2" v="0b010"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_SPMU) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        Undefined();
    elsif MDSCR_EL1().EnSPM == '0' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif !ELIsInHost(EL0) &amp;&amp; SPMACCESSR_EL1()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        if EL2Enabled() &amp;&amp; HCR_EL2().TGE == '1' then
            AArch64_SystemAccessTrap(EL2, 0x18);
        else
            AArch64_SystemAccessTrap(EL1, 0x18);
        end;
    elsif EL2Enabled() &amp;&amp; !ELIsInHost(EL0) &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMCNTEN == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().EnSPM == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t);
    end;
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMCNTEN == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().EnSPM == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t);
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t);
    end;
elsif PSTATE.EL == EL3 then
    SPMCNTENCLR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t);
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>