<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>SPMDEVARCH_EL1</reg_short_name>
        
        <reg_long_name>System Performance Monitors Device Architecture Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_SPMU is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Provides discovery information for System PMU &lt;s&gt;.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Unknown</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>SPMDEVARCH_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_32" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>32</field_lsb>
    <rel_range>63:32</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-31_21" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ARCHITECT</field_name>
    <field_msb>31</field_msb>
    <field_lsb>21</field_lsb>
    <rel_range>31:21</rel_range>
    <field_description order="before">
      <para>Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-20_20" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>PRESENT</field_name>
    <field_msb>20</field_msb>
    <field_lsb>20</field_lsb>
    <rel_range>20</rel_range>
    <field_description order="before">
      <para>DEVARCH present. Defines that SPMDEVARCH_EL1 register is present.</para>
    </field_description>
    <field_description order="after">
      <para>If SPMDEVARCH_EL1 is not present, the register is <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Device Architecture information not present.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Device Architecture information present.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
  </field>
  <field id="fieldset_0-19_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>REVISION</field_name>
    <field_msb>19</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>19:16</rel_range>
    <field_description order="before">
      <para>Revision. Defines the architecture revision of the component.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-15_12" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ARCHVER</field_name>
    <field_msb>15</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>15:12</rel_range>
    <field_description order="before">
      <para>Architecture Version. Defines the architecture version of the component.</para>
    </field_description>
    <field_description order="after"><para>SPMDEVARCH_EL1.ARCHVER and SPMDEVARCH_EL1.ARCHPART are also defined as a single field, SPMDEVARCH_EL1.ARCHID, so that SPMDEVARCH_EL1.ARCHVER is SPMDEVARCH_EL1.ARCHID[15:12].</para>
<para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para></field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-11_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ARCHPART</field_name>
    <field_msb>11</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>11:0</rel_range>
    <field_description order="before">
      <para>Architecture Part. Defines the architecture of the component.</para>
    </field_description>
    <field_description order="after"><para>SPMDEVARCH_EL1.ARCHVER and SPMDEVARCH_EL1.ARCHPART are also defined as a single field, SPMDEVARCH_EL1.ARCHID, so that SPMDEVARCH_EL1.ARCHPART is SPMDEVARCH_EL1.ARCHID[11:0].</para>
<para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para></field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_32" msb="63" lsb="32"/>
  <fieldat id="fieldset_0-31_21" msb="31" lsb="21"/>
  <fieldat id="fieldset_0-20_20" msb="20" lsb="20"/>
  <fieldat id="fieldset_0-19_16" msb="19" lsb="16"/>
  <fieldat id="fieldset_0-15_12" msb="15" lsb="12"/>
  <fieldat id="fieldset_0-11_0" msb="11" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>To access SPMDEVARCH_EL1 for System PMU &lt;s&gt;, set <register_link state="AArch64" id="AArch64-spmselr_el0.xml">SPMSELR_EL0</register_link>.SYSPMUSEL to s.</para>

      </access_permission_text>
      <access_permission_text>
        <para>SPMDEVARCH_EL1 reads-as-zero if any of the following are true:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>System PMU &lt;s&gt; is not implemented.</content>
</listitem><listitem><content>System PMU &lt;s&gt; does not implement SPMDEVARCH_EL1.</content>
</listitem></list>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS SPMDEVARCH_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, SPMDEVARCH_EL1</access_instruction>
                
                <enc n="op0" v="0b10"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b1001"/>
                
                <enc n="CRm" v="0b1101"/>
                
                <enc n="op2" v="0b101"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_SPMU) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; ((HaveEL(EL3) &amp;&amp; SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMID == '0') then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2().EnSPM == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMDEVARCH_EL1(UInt(SPMSELR_EL0().SYSPMUSEL));
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3().EnPM2 == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    elsif HaveEL(EL3) &amp;&amp; SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = SPMDEVARCH_EL1(UInt(SPMSELR_EL0().SYSPMUSEL));
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = SPMDEVARCH_EL1(UInt(SPMSELR_EL0().SYSPMUSEL));
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>