SPMSELR_EL0 System Performance Monitors Select Register when FEAT_SPMU is implemented and FEAT_AA64 is implemented Selects the System PMU and event counter registers to access. Unknown SPMSELR_EL0 is a 64-bit register. 63 10 63:10 Reserved, RES0. SYSPMUSEL 9 4 9:4 System PMU Select. Selects a System PMU <s> to access. Values 0x20 to 0x3F are reserved. AU 3 2 3:2 Reserved, RES0. BANK 1 0 1:0 System PMU bank access control. Selects a bank of 16 System PMU event counters and related controls to access. 0b00 Select event counters 0 to 15. 0b01 Select event counters 16 to 31. 0b10 Select event counters 32 to 47. 0b11 Select event counters 48 to 63. AU MRS <Xt>, SPMSELR_EL0 if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif MDSCR_EL1().EnSPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMSELR_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMSELR_EL0(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMSELR_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMSELR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMSELR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SPMSELR_EL0(); end; MSR SPMSELR_EL0, <Xt> if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif MDSCR_EL1().EnSPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMSELR_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SPMSELR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMSELR_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SPMSELR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SPMSELR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL3 then SPMSELR_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel