SPSR_EL1 Saved Program Status Register (EL1) when FEAT_AA64 is implemented SPSR_svc Architectural AArch32 31 0 31 0 31 0 31 0 Holds the saved process state when an exception is taken to EL1. Special SPSR_EL1 is a 64-bit register. When FEAT_AA32 is implemented and exception taken from AArch32 state exception taken from AArch32 An exception return from EL1 using AArch64 makes SPSR_EL1 become UNKNOWN. 63 37 63:37 Reserved, RES0. UINJ 36 36 0 Inject Undefined Instruction exception. Set to 0 on taking an exception to EL1, and copied to PSTATE.UINJ on executing an exception return operation in EL1. AU When FEAT_UINJ is implemented 36 36 36 Reserved, RES0. Otherwise 35 32 35:32 Reserved, RES0. N 31 31 31 Negative Condition flag. Set to the value of PSTATE.N on taking an exception to EL1, and copied to PSTATE.N on executing an exception return operation in EL1. AU Z 30 30 30 Zero Condition flag. Set to the value of PSTATE.Z on taking an exception to EL1, and copied to PSTATE.Z on executing an exception return operation in EL1. AU C 29 29 29 Carry Condition flag. Set to the value of PSTATE.C on taking an exception to EL1, and copied to PSTATE.C on executing an exception return operation in EL1. AU V 28 28 28 Overflow Condition flag. Set to the value of PSTATE.V on taking an exception to EL1, and copied to PSTATE.V on executing an exception return operation in EL1. AU Q 27 27 27 Overflow or saturation flag. Set to the value of PSTATE.Q on taking an exception to EL1, and copied to PSTATE.Q on executing an exception return operation in EL1. AU IT 26 25 15:10, 26:25 If-Then. Set to the value of PSTATE.IT on taking an exception to EL1, and copied to PSTATE.IT on executing an exception return operation in EL1. On executing an exception return operation in EL1, SPSR_EL1.IT must contain a value that is valid for the instruction being returned to. The IT field is split as follows: IT[1:0] is SPSR_EL1[26:25]. IT[7:2] is SPSR_EL1[15:10]. 15 10 26 25 AU DIT 24 24 0 Data Independent Timing. Set to the value of PSTATE.DIT on taking an exception to EL1, and copied to PSTATE.DIT on executing an exception return operation in EL1. AU When FEAT_DIT is implemented 24 24 24 Reserved, RES0. Otherwise SSBS 23 23 0 Speculative Store Bypass. Set to the value of PSTATE.SSBS on taking an exception to EL1, and copied to PSTATE.SSBS on executing an exception return operation in EL1. AU When FEAT_SSBS is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Set to the value of PSTATE.PAN on taking an exception to EL1, and copied to PSTATE.PAN on executing an exception return operation in EL1. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise SS 21 21 21 Software Step. Set to the value of PSTATE.SS on taking an exception to EL1, and conditionally copied to PSTATE.SS on executing an exception return operation in EL1. AU IL 20 20 20 Illegal Execution state. Set to the value of PSTATE.IL on taking an exception to EL1, and copied to PSTATE.IL on executing an exception return operation in EL1. AU GE 19 16 19:16 Greater than or Equal flags. Set to the value of PSTATE.GE on taking an exception to EL1, and copied to PSTATE.GE on executing an exception return operation in EL1. AU IT[7:2] 15 10 15:10, 26:25 This field is bits[7:2] of IT[7:0]. See IT[1:0] for the field description. E 9 9 9 Endianness. Set to the value of PSTATE.E on taking an exception to EL1, and copied to PSTATE.E on executing an exception return operation in EL1. If the implementation does not support big-endian operation, SPSR_EL1.E is RES0. If the implementation does not support little-endian operation, SPSR_EL1.E is RES1. On executing an exception return operation in EL1, if the implementation does not support big-endian operation at the Exception level being returned to, SPSR_EL1.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, SPSR_EL1.E is RES1. AU A 8 8 8 SError exception mask. Set to the value of PSTATE.A on taking an exception to EL1, and copied to PSTATE.A on executing an exception return operation in EL1. AU I 7 7 7 IRQ interrupt mask. Set to the value of PSTATE.I on taking an exception to EL1, and copied to PSTATE.I on executing an exception return operation in EL1. AU F 6 6 6 FIQ interrupt mask. Set to the value of PSTATE.F on taking an exception to EL1, and copied to PSTATE.F on executing an exception return operation in EL1. AU T 5 5 5 T32 Instruction set state. Set to the value of PSTATE.T on taking an exception to EL1, and copied to PSTATE.T on executing an exception return operation in EL1. AU M[4] 4 4 4 Execution state. Set to 1, the value of PSTATE.nRW, on taking an exception to EL1 from AArch32 state, and copied to PSTATE.nRW on executing an exception return operation in EL1. 0b1 AArch32 execution state. AU M[3:0] 3 0 3:0 AArch32 Mode. Set to the value of PSTATE.M[3:0] on taking an exception to EL1, and copied to PSTATE.M[3:0] on executing an exception return operation in EL1. Other values are reserved. If SPSR_EL1.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, executing an exception return operation in EL1 is an illegal return event, as described in 'Illegal return events from AArch64 state'. 0b0000 User. 0b0001 FIQ. 0b0010 IRQ. 0b0011 Supervisor. 0b0111 Abort. 0b1011 Undefined. 0b1111 System. AU When exception taken from AArch64 state exception taken from AArch64 An exception return from EL1 using AArch64 makes SPSR_EL1 become UNKNOWN. 63 37 63:37 Reserved, RES0. UINJ 36 36 0 Inject Undefined Instruction exception. Set to 0 on taking an exception to EL1, and copied to PSTATE.UINJ on executing an exception return operation in EL1. AU When FEAT_UINJ is implemented 36 36 36 Reserved, RES0. Otherwise PACM 35 35 0 PACM. Set to the value of PSTATE.PACM on taking an exception to EL1, and copied to PSTATE.PACM on executing an exception return operation in EL1. AU When FEAT_PAuth_LR is implemented 35 35 35 Reserved, RES0. Otherwise EXLOCK 34 34 0 Exception return state lock. Set to the value of PSTATE.EXLOCK on taking an exception to EL1, and copied to PSTATE.EXLOCK on executing an exception return operation in EL1. AU When FEAT_GCS is implemented 34 34 34 Reserved, RES0. Otherwise 33 33 33 Reserved, RES0. PM 32 32 0 Profiling exception mask bit. Set to the value of PSTATE.PM on taking an exception to EL1, and copied to PSTATE.PM on executing an exception return operation in EL1. AU When FEAT_EBEP is implemented 32 32 32 Reserved, RES0. Otherwise N 31 31 31 Negative Condition flag. Set to the value of PSTATE.N on taking an exception to EL1, and copied to PSTATE.N on executing an exception return operation in EL1. AU Z 30 30 30 Zero Condition flag. Set to the value of PSTATE.Z on taking an exception to EL1, and copied to PSTATE.Z on executing an exception return operation in EL1. AU C 29 29 29 Carry Condition flag. Set to the value of PSTATE.C on taking an exception to EL1, and copied to PSTATE.C on executing an exception return operation in EL1. AU V 28 28 28 Overflow Condition flag. Set to the value of PSTATE.V on taking an exception to EL1, and copied to PSTATE.V on executing an exception return operation in EL1. AU 27 26 27:26 Reserved, RES0. TCO 25 25 0 Tag Check Override. Set to the value of PSTATE.TCO on taking an exception to EL1, and copied to PSTATE.TCO on executing an exception return operation in EL1. AU When FEAT_MTE is implemented 25 25 25 Reserved, RES0. Otherwise DIT 24 24 0 Data Independent Timing. Set to the value of PSTATE.DIT on taking an exception to EL1, and copied to PSTATE.DIT on executing an exception return operation in EL1. AU When FEAT_DIT is implemented 24 24 24 Reserved, RES0. Otherwise UAO 23 23 0 User Access Override. Set to the value of PSTATE.UAO on taking an exception to EL1, and copied to PSTATE.UAO on executing an exception return operation in EL1. AU When FEAT_UAO is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Set to the value of PSTATE.PAN on taking an exception to EL1, and copied to PSTATE.PAN on executing an exception return operation in EL1. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise SS 21 21 21 Software Step. Set to the value of PSTATE.SS on taking an exception to EL1, and conditionally copied to PSTATE.SS on executing an exception return operation in EL1. AU IL 20 20 20 Illegal Execution state. Set to the value of PSTATE.IL on taking an exception to EL1, and copied to PSTATE.IL on executing an exception return operation in EL1. AU 19 14 19:14 Reserved, RES0. ALLINT 13 13 0 All IRQ or FIQ interrupts mask. Set to the value of PSTATE.ALLINT on taking an exception to EL1, and copied to PSTATE.ALLINT on executing an exception return operation in EL1. AU When FEAT_NMI is implemented 13 13 13 Reserved, RES0. Otherwise SSBS 12 12 0 Speculative Store Bypass. Set to the value of PSTATE.SSBS on taking an exception to EL1, and copied to PSTATE.SSBS on executing an exception return operation in EL1. AU When FEAT_SSBS is implemented 12 12 12 Reserved, RES0. Otherwise BTYPE 11 10 1:0 Branch Type Indicator. Set to the value of PSTATE.BTYPE on taking an exception to EL1, and copied to PSTATE.BTYPE on executing an exception return operation in EL1. AU When FEAT_BTI is implemented 11 10 11:10 Reserved, RES0. Otherwise D 9 9 9 Debug exception mask. Set to the value of PSTATE.D on taking an exception to EL1, and copied to PSTATE.D on executing an exception return operation in EL1. AU A 8 8 8 SError exception mask. Set to the value of PSTATE.A on taking an exception to EL1, and copied to PSTATE.A on executing an exception return operation in EL1. AU I 7 7 7 IRQ interrupt mask. Set to the value of PSTATE.I on taking an exception to EL1, and copied to PSTATE.I on executing an exception return operation in EL1. AU F 6 6 6 FIQ interrupt mask. Set to the value of PSTATE.F on taking an exception to EL1, and copied to PSTATE.F on executing an exception return operation in EL1. AU 5 5 5 Reserved, RES0. M[4] 4 4 4 Execution state. Set to 0, the value of PSTATE.nRW, on taking an exception to EL1 from AArch64 state, and copied to PSTATE.nRW on executing an exception return operation in EL1. 0b0 AArch64 execution state. AU M[3:0] 3 0 3:0 AArch64 Exception level and selected Stack Pointer. Other values are reserved. If SPSR_EL1.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, executing an exception return operation in EL1 is an illegal return event, as described in 'Illegal return events from AArch64 state'. The bits in this field are interpreted as follows: M[3:2]: On an exception to EL1: If the exception is taken from EL0: M[3:2] is set to the value of PSTATE.EL on taking an exception to EL1. If the exception is taken from EL1: If the Effective value of HCR_EL2.{NV, NV1} is not {1,0} and the Effective value of HCR_EL2.{NV, NV2} is not {1,1}, then M[3:2] is set to the value of PSTATE.EL on taking an exception to EL1. If the Effective value of HCR_EL2.{NV, NV1} is {1,0} or if the Effective value of HCR_EL2.{NV, NV2} is {1,1}, then M[3:2] is set to 0b10. M[3:2] is copied to PSTATE.EL on executing a legal exception return operation in EL1. M[1] is unused and is 0 for all non-reserved values. M[0] is set to the value of PSTATE.SP on taking an exception to EL1 and copied to PSTATE.SP on executing an exception return operation in EL1. 0b0000 EL0. 0b0100 EL1 with SP_EL0 (EL1t). 0b0101 EL1 with SP_EL1 (EL1h). 0b1000 EL1 with SP_EL0 (EL1t) and either HCR_EL2.{NV, NV1} is {1,0} or HCR_EL2.{NV, NV2} is {1,1}. 0b1001 EL1 with SP_EL1 (EL1h) and either HCR_EL2.{NV, NV1} is {1,0} or HCR_EL2.{NV, NV2} is {1,1}. AU When FEAT_AA32 is implemented and exception taken from AArch32 state When exception taken from AArch64 state When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name SPSR_EL1 or SPSR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. The MSR (register) and MRS instructions used to access SPSR_EL1 are data-independent-time instructions as described in About PSTATE.DIT. MRS <Xt>, SPSR_EL1 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '011' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x160); else X{64}(t) = SPSR_EL1(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = SPSR_EL2(); else X{64}(t) = SPSR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = SPSR_EL1(); end; MSR SPSR_EL1, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && !(EffectiveHCR_EL2_NVx() IN {'x11'}) then EXLOCKException(); elsif EffectiveHCR_EL2_NVx() == '011' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x160) = X{64}(t); else SPSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && ELIsInHost(EL2) then EXLOCKException(); elsif ELIsInHost(EL2) then SPSR_EL2() = X{64}(t); else SPSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then SPSR_EL1() = X{64}(t); end; MRS <Xt>, SPSR_EL12 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x160); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X{64}(t) = SPSR_EL1(); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = SPSR_EL1(); else Undefined(); end; end; MSR SPSR_EL12, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x160) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then SPSR_EL1() = X{64}(t); else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SPSR_EL1() = X{64}(t); else Undefined(); end; end; MRS <Xt>, SPSR_EL2 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = SPSR_EL1(); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = SPSR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = SPSR_EL2(); end; MSR SPSR_EL2, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' && EffectiveHCR_EL2_NVx() IN {'xx1'} then EXLOCKException(); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then SPSR_EL1() = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if IsFeatureImplemented(FEAT_GCS) && GetCurrentEXLOCKEN() && !Halted() && PSTATE.EXLOCK == '1' then EXLOCKException(); else SPSR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then SPSR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel