SPSR_fiq Saved Program Status Register (FIQ mode) when FEAT_AA64 is implemented SPSR_fiq Architectural AArch32 31 0 31 0 31 0 31 0 Holds the saved process state when an exception is taken to FIQ mode. Special If EL1 only supports execution in AArch64 state, this register is RES0 from EL2 and EL3. SPSR_fiq is a 64-bit register. When FEAT_AA32EL1 is not implemented 63 0 63:0 Reserved, RES0. 63 32 63:32 Reserved, RES0. N 31 31 31 Negative Condition flag. Set to the value of PSTATE.N on taking an exception to FIQ mode, and copied to PSTATE.N on executing an exception return operation in FIQ mode. AU Z 30 30 30 Zero Condition flag. Set to the value of PSTATE.Z on taking an exception to FIQ mode, and copied to PSTATE.Z on executing an exception return operation in FIQ mode. AU C 29 29 29 Carry Condition flag. Set to the value of PSTATE.C on taking an exception to FIQ mode, and copied to PSTATE.C on executing an exception return operation in FIQ mode. AU V 28 28 28 Overflow Condition flag. Set to the value of PSTATE.V on taking an exception to FIQ mode, and copied to PSTATE.V on executing an exception return operation in FIQ mode. AU Q 27 27 27 Overflow or saturation flag. Set to the value of PSTATE.Q on taking an exception to FIQ mode, and copied to PSTATE.Q on executing an exception return operation in FIQ mode. AU IT 26 25 15:10, 26:25 If-Then. Set to the value of PSTATE.IT on taking an exception to FIQ mode, and copied to PSTATE.IT on executing an exception return operation in FIQ mode. On executing an exception return operation in FIQ mode, SPSR_fiq.IT must contain a value that is valid for the instruction being returned to. The IT field is split as follows: IT[1:0] is SPSR_fiq[26:25]. IT[7:2] is SPSR_fiq[15:10]. 15 10 26 25 AU J 24 24 24 RES0. In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. Armv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state. SSBS 23 23 0 Speculative Store Bypass. Set to the value of PSTATE.SSBS on taking an exception to FIQ mode, and copied to PSTATE.SSBS on executing an exception return operation in FIQ mode. AU When FEAT_SSBS is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Set to the value of PSTATE.PAN on taking an exception to FIQ mode, and copied to PSTATE.PAN on executing an exception return operation in FIQ mode. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise DIT 21 21 0 Data Independent Timing. Set to the value of PSTATE.DIT on taking an exception to FIQ mode, and copied to PSTATE.DIT on executing an exception return operation in FIQ mode. AU When FEAT_DIT is implemented 21 21 21 Reserved, RES0. Otherwise IL 20 20 20 Illegal Execution state. Set to the value of PSTATE.IL on taking an exception to FIQ mode, and copied to PSTATE.IL on executing an exception return operation in FIQ mode. AU GE 19 16 19:16 Greater than or Equal flags. Set to the value of PSTATE.GE on taking an exception to FIQ mode, and copied to PSTATE.GE on executing an exception return operation in FIQ mode. AU IT[7:2] 15 10 15:10, 26:25 This field is bits[7:2] of IT[7:0]. See IT[1:0] for the field description. E 9 9 9 Endianness. Set to the value of PSTATE.E on taking an exception to FIQ mode, and copied to PSTATE.E on executing an exception return operation in FIQ mode. If the implementation does not support big-endian operation, SPSR_fiq.E is RES0. If the implementation does not support little-endian operation, SPSR_fiq.E is RES1. On executing an exception return operation in FIQ mode, if the implementation does not support big-endian operation at the Exception level being returned to, SPSR_fiq.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, SPSR_fiq.E is RES1. AU A 8 8 8 SError exception mask. Set to the value of PSTATE.A on taking an exception to FIQ mode, and copied to PSTATE.A on executing an exception return operation in FIQ mode. AU I 7 7 7 IRQ interrupt mask. Set to the value of PSTATE.I on taking an exception to FIQ mode, and copied to PSTATE.I on executing an exception return operation in FIQ mode. AU F 6 6 6 FIQ interrupt mask. Set to the value of PSTATE.F on taking an exception to FIQ mode, and copied to PSTATE.F on executing an exception return operation in FIQ mode. AU T 5 5 5 T32 Instruction set state. Set to the value of PSTATE.T on taking an exception to FIQ mode, and copied to PSTATE.T on executing an exception return operation in FIQ mode. AU M[4:0] 4 0 4:0 Mode. Set to the value of PSTATE.M[4:0] on taking an exception to FIQ mode, and copied to PSTATE.M[4:0] on executing an exception return operation in FIQ mode. Other values are reserved. If SPSR_fiq.M[4:0] has a Reserved value, or a value for an unimplemented Exception level, executing an exception return operation in FIQ mode is an illegal return event, as described in 'Illegal return events from AArch32 state'. 0b10000 User. 0b10001 FIQ. 0b10010 IRQ. 0b10011 Supervisor. 0b10111 Abort. 0b11011 Undefined. 0b11111 System. AU When FEAT_AA32EL1 is not implemented The MSR (register) and MRS instructions used to access SPSR_fiq are data-independent-time instructions as described in About PSTATE.DIT. MRS <Xt>, SPSR_fiq if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = SPSR_fiq(); elsif PSTATE.EL == EL3 then X{64}(t) = SPSR_fiq(); end; MSR SPSR_fiq, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then SPSR_fiq() = X{64}(t); elsif PSTATE.EL == EL3 then SPSR_fiq() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel