<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
<!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<!--The data contained in this document is preliminary and subject to change or correction following further review. -->
<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>SSBS</reg_short_name>
        
        <reg_long_name>Speculative Store Bypass Safe</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_SSBS2 is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Allows access to the Speculative Store Bypass Safe bit.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>PSTATE</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>SSBS is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_13" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>13</field_lsb>
    <rel_range>63:13</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-12_12" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>SSBS</field_name>
    <field_msb>12</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>12</rel_range>
    <field_description order="before"><para>Speculative Store Bypass Safe.</para>
<para>Prohibits speculative loads or stores which might practically allow a cache timing side channel.</para>
<para>A speculative value in a register is used in a potentially speculatively exploitable manner if it is used to form an address, generate condition codes, or generate SVE predicate values to be used by other instructions in the speculative sequence or if the execution timing of any other instructions in the speculative sequence is a function of the data loaded under speculation.</para></field_description>
    <field_description order="after">
      <para>The value of this bit is set to the value in the SCTLR_ELx.DSSBS field on taking an exception to ELx.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Hardware is not permitted to use speculative register values in a potentially speculatively exploitable manner if the speculative read that loads the register is from earlier in the coherence order than the entry generated by the latest store to that location using the same virtual address as the load instruction.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>When the value of PSTATE.SSBS is 1, hardware is permitted to use speculative register values in a potentially speculatively exploitable manner if the speculative read that loads the register is from earlier in the coherence order than the entry generated by the latest store to that location using the same virtual address as the load instruction.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Warm" impdef="true">
        <field_reset_standard_text>ID</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <field id="fieldset_0-11_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>11</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>11:0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_13" msb="63" lsb="13"/>
  <fieldat id="fieldset_0-12_12" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-11_0" msb="11" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    
        
        <access_mechanism accessor="MRS SSBS" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, SSBS</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b0100"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b110"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_SSBS2) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    X{64}(t) = Zeros{51} :: PSTATE.SSBS :: Zeros{12};
elsif PSTATE.EL == EL1 then
    X{64}(t) = Zeros{51} :: PSTATE.SSBS :: Zeros{12};
elsif PSTATE.EL == EL2 then
    X{64}(t) = Zeros{51} :: PSTATE.SSBS :: Zeros{12};
elsif PSTATE.EL == EL3 then
    X{64}(t) = Zeros{51} :: PSTATE.SSBS :: Zeros{12};
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister SSBS" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR SSBS, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b0100"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b110"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_SSBS2) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    PSTATE.SSBS = X{64}(t)[12];
elsif PSTATE.EL == EL1 then
    PSTATE.SSBS = X{64}(t)[12];
elsif PSTATE.EL == EL2 then
    PSTATE.SSBS = X{64}(t)[12];
elsif PSTATE.EL == EL3 then
    PSTATE.SSBS = X{64}(t)[12];
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRimmediate SSBS" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR SSBS, #&lt;imm&gt;</access_instruction>
                
                <enc n="op0" v="0b00"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b0100"/>
                
                <enc n="op2" v="0b001"/>
            </encoding>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>