<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>TCO</reg_short_name>
        
        <reg_long_name>Tag Check Override</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_MTE is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>When <xref filename="A_armv8_architecture_extensions.fm" linkend="FEAT_MTE">FEAT_MTE</xref> is implemented, this register allows tag checks to be disabled globally.</para>

      </purpose_text>
      <purpose_text>
        <para>When <xref linkend="#FEAT_MTE2">FEAT_MTE2</xref> is not implemented, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> if accesses to this register access PSTATE.TCO or are RAZ/WI.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>PSTATE</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>TCO is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_26" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>63</field_msb>
    <field_lsb>26</field_lsb>
    <rel_range>63:26</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-25_25" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>TCO</field_name>
    <field_msb>25</field_msb>
    <field_lsb>25</field_lsb>
    <rel_range>25</rel_range>
    <field_description order="before">
      <para>Allows memory tag checks to be globally disabled.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Loads and Stores are not affected by this control.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Loads and Stores are unchecked.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
  </field>
  <field id="fieldset_0-24_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>24</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>24:0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_26" msb="63" lsb="26"/>
  <fieldat id="fieldset_0-25_25" msb="25" lsb="25"/>
  <fieldat id="fieldset_0-24_0" msb="24" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>For information about the operation of the MSR (immediate) accessor, see <xref filename="C_a64_base_instruction_descriptions.fm" linkend="A64.instructions.MSR_imm">MSR (immediate)</xref>.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS TCO" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, TCO</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b0100"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b111"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_MTE) then
    Undefined();
elsif PSTATE.EL == EL0 then
    X{64}(t) = Zeros{38} :: PSTATE.TCO :: Zeros{25};
elsif PSTATE.EL == EL1 then
    X{64}(t) = Zeros{38} :: PSTATE.TCO :: Zeros{25};
elsif PSTATE.EL == EL2 then
    X{64}(t) = Zeros{38} :: PSTATE.TCO :: Zeros{25};
elsif PSTATE.EL == EL3 then
    X{64}(t) = Zeros{38} :: PSTATE.TCO :: Zeros{25};
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRregister TCO" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR TCO, &lt;Xt&gt;</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b0100"/>
                
                <enc n="CRm" v="0b0010"/>
                
                <enc n="op2" v="0b111"/>
            </encoding>
            <access_permission>
                <ps name="MSRregister" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_MTE) then
    Undefined();
elsif PSTATE.EL == EL0 then
    PSTATE.TCO = X{64}(t)[25];
elsif PSTATE.EL == EL1 then
    PSTATE.TCO = X{64}(t)[25];
elsif PSTATE.EL == EL2 then
    PSTATE.TCO = X{64}(t)[25];
elsif PSTATE.EL == EL3 then
    PSTATE.TCO = X{64}(t)[25];
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>
    
        
        <access_mechanism accessor="MSRimmediate TCO" type="SystemAccessor">
            <encoding>
            <access_instruction>MSR TCO, #&lt;imm&gt;</access_instruction>
                
                <enc n="op0" v="0b00"/>
                
                <enc n="op1" v="0b011"/>
                
                <enc n="CRn" v="0b0100"/>
                
                <enc n="op2" v="0b100"/>
            </encoding>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>