TCR2_EL1 Extended Translation Control Register (EL1) when FEAT_TCR2 is implemented and FEAT_AA64 is implemented The control register for stage 1 of the EL1&0 translation regime. Memory TCR2_EL1 is a 64-bit register. Unless stated otherwise, all the bits in TCR2_EL1 are permitted to be cached in a TLB. 63 22 63:22 Reserved, RES0. FNGNA1 21 21 0 Force non-global for unassured translations using TTBR1_EL1. This bit is permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 This bit has no effect on the interpretation of the nG bit. 0b1 Translations using TTBR1_EL1 are treated as non-global regardless of the value of the nG bit if all of the following is true: The translation is for the EL1&0 translation regime. Stage 1 and stage 2 translation are enabled. Protection is enabled. The final stage 1 translation using the descriptor does not have the Assured Translation property. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.FNGNA1 == '1' RO When FEAT_THE is implemented 21 21 21 Reserved, RES0. Otherwise FNGNA0 20 20 0 Force non-global for unassured translations using TTBR0_EL1. This bit is permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 This bit has no effect on the interpretation of the nG bit. 0b1 Translations using TTBR0_EL1 are treated as non-global regardless of the value of the nG bit if all of the following is true: The translation is for the EL1&0 translation regime. Stage 1 and stage 2 translation are enabled. Protection is enabled. The final stage 1 translation using the descriptor does not have the Assured Translation property. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.FNGNA0 == '1' RO When FEAT_THE is implemented 20 20 20 Reserved, RES0. Otherwise 19 19 19 Reserved, RES0. FNG1 18 18 0 Force non-global translations for TTBR1_EL1. This bit is permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 This bit has no effect on the interpretation of the nG bit. 0b1 Translations using TTBR1_EL1 are treated as non-global regardless of the value of the nG bit. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.FNG1 == '1' RO When FEAT_ASID2 is implemented 18 18 18 Reserved, RES0. Otherwise FNG0 17 17 0 Force non-global translations for TTBR0_EL1. This bit is permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 This bit has no effect on the interpretation of the nG bit. 0b1 Translations using TTBR0_EL1 are treated as non-global regardless of the value of the nG bit. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.FNG0 == '1' RO When FEAT_ASID2 is implemented 17 17 17 Reserved, RES0. Otherwise A2 16 16 0 Enable use of two ASIDs. This bit is permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Use of two ASIDs is disabled. 0b1 Use of two ASIDs is enabled. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.A2 == '1' RO When FEAT_ASID2 is implemented 16 16 16 Reserved, RES0. Otherwise DisCH1 15 15 0 Disable the Contiguous bit for the Start Table for TTBR1_EL1. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL1 is not affected by this field. 0b1 The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL1 is treated as 0. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.DisCH1 == '1' RO When FEAT_D128 is implemented and TCR2_EL1.D128 == '1' 15 15 15 Reserved, RES0. Otherwise DisCH0 14 14 0 Disable the Contiguous bit for the Start Table for TTBR0_EL1. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL1 is not affected by this field. 0b1 The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL1 is treated as 0. AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.DisCH0 == '1' RO When FEAT_D128 is implemented and TCR2_EL1.D128 == '1' 14 14 14 Reserved, RES0. Otherwise 13 12 13:12 Reserved, RES0. HAFT 11 11 0 Hardware managed Access Flag for Table descriptors. Enables the Hardware managed Access Flag for Table descriptors. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Hardware managed Access Flag for Table descriptors is disabled. 0b1 Hardware managed Access Flag for Table descriptors is enabled. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.HAFT == '1' RO When FEAT_HAFT is implemented 11 11 11 Reserved, RES0. Otherwise PTTWI 10 10 0 Permit Translation table walk Incoherence. Permits RCWS instructions to generate writes that have the Reduced Coherence property. This bit is permitted to be implemented as a read-only bit with a fixed value of 0. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Write accesses generated by RCWS at EL1&0 do not have the Reduced Coherence property. 0b1 Write accesses generated by RCWS at EL1&0 have the Reduced Coherence property if HCRX_EL2.PTTWI is 1. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.PTTWI == '1' RO When FEAT_THE is implemented 10 10 10 Reserved, RES0. Otherwise 9 6 9:6 Reserved, RES0. D128 5 5 0 Enables VMSAv9-128 translation system. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Translation system follows VMSAv8-64 translation process. 0b1 Translation system follows VMSAv9-128 translation process. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.D128 == '1' RO When FEAT_D128 is implemented 5 5 5 Reserved, RES0. Otherwise AIE 4 4 0 Enable Attribute Indexing Extension. This field is RES1 when TCR2_EL1.D128 is 1. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Attribute Indexing Extension Disabled. 0b1 Attribute Indexing Extension Enabled. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.AIE == '1' RO When FEAT_AIE is implemented 4 4 4 Reserved, RES0. Otherwise POE 3 3 0 Enables Permission Overlays for privileged accesses from EL1&0 translation regime. This bit is not permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Permission overlay disabled for EL1 access in stage 1 of EL1&0 translation regime. 0b1 Permission overlay enabled for EL1 access in stage 1 of EL1&0 translation regime. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.POE == '1' RO When FEAT_S1POE is implemented 3 3 3 Reserved, RES0. Otherwise E0POE 2 2 0 Enables Permission Overlays for unprivileged accesses from EL1&0 translation regime. This bit is not permitted to be cached in a TLB. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Permission overlay disabled for EL0 access in stage 1 of EL1&0 translation regime. 0b1 Permission overlay enabled for EL0 access in stage 1 of EL1&0 translation regime. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.E0POE == '1' RO When FEAT_S1POE is implemented 2 2 2 Reserved, RES0. Otherwise PIE 1 1 0 Enables usage of Indirect Permission Scheme. This field is RES1 when TCR2_EL1.D128 is 1. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 Direct permission model. 0b1 Indirect permission model. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.PIE == '1' RO When FEAT_S1PIE is implemented 1 1 1 Reserved, RES0. Otherwise PnCH 0 0 0 Protected attribute enable. Enables use of bit[52] of the stage 1 translation table entries as the Protected bit, for translations using TTBRn_EL1. If bit[52] is used as the Protected bit, it is not used as the Contiguous bit. This field is RES0 when TCR2_EL1.D128 is 1. This field is ignored by the PE and treated as zero when any of the following are true: All of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCRX_EL2.TCR2En is 0. EL3 is implemented and SCR_EL3.TCR2En == 0. 0b0 For translations using TTBRn_EL1, bit[52] of each stage 1 translation table entry is not the Protected bit. 0b1 For translations using TTBRn_EL1, bit[52] of each stage 1 translation table entry is the Protected bit. '0' AU FEAT_SRMASK is implemented EL1 is the current Exception level IsSystemRegisterMaskingEnabled(EL1) TCR2MASK_EL1.PnCH == '1' RO When FEAT_THE is implemented 0 0 0 Reserved, RES0. Otherwise When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TCR2_EL1 or TCR2_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. If FEAT_SRMASK is implemented, accesses to TCR2_EL1 are masked by TCR2MASK_EL1. MRS <Xt>, TCR2_EL1 if !(IsFeatureImplemented(FEAT_TCR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().TCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().TCR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x270); else X{64}(t) = TCR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCR2_EL2(); else X{64}(t) = TCR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCR2_EL1(); end; MSR TCR2_EL1, <Xt> if !(IsFeatureImplemented(FEAT_TCR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().TCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().TCR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x270) = X{64}(t); else TCR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then TCR2_EL2() = X{64}(t); else TCR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCR2_EL1() = X{64}(t); end; MRS <Xt>, TCR2_EL12 if !(IsFeatureImplemented(FEAT_TCR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x270); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TCR2_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = TCR2_EL1(); else Undefined(); end; end; MSR TCR2_EL12, <Xt> When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_TCR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x270) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TCR2_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TCR2_EL1() = X{64}(t); else Undefined(); end; end; MRS <Xt>, TCR2ALIAS_EL1 When FEAT_SRMASK is implemented if !(IsFeatureImplemented(FEAT_TCR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TRVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTCR2ALIAS_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().TCR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x270); else X{64}(t) = TCR2_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCR2_EL2(); else X{64}(t) = TCR2_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCR2_EL1(); end; MSR TCR2ALIAS_EL1, <Xt> When FEAT_SRMASK is implemented if !(IsFeatureImplemented(FEAT_TCR2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().TVM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nTCR2ALIAS_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().TCR2En == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x270) = X{64}(t); else TCR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TCR2En == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TCR2En == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then TCR2_EL2() = X{64}(t); else TCR2_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCR2_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel