TCR2MASK_EL1 Extended Translation Control Masking Register (EL1) when FEAT_SRMASK is implemented and FEAT_AA64 is implemented Mask register to prevent updates of fields in TCR2_EL1 on writes to TCR2_EL1 or TCR2ALIAS_EL1. Other TCR2MASK_EL1 is a 64-bit register. 63 22 63:22 Reserved, RES0. FNGNA1 21 21 0 Mask bit for FNGNA1. 0b0 TCR2_EL1.FNGNA1 is writable. 0b1 TCR2_EL1.FNGNA1 is not writable. '0' AU When FEAT_THE is implemented 21 21 21 Reserved, RES0. Otherwise FNGNA0 20 20 0 Mask bit for FNGNA0. 0b0 TCR2_EL1.FNGNA0 is writable. 0b1 TCR2_EL1.FNGNA0 is not writable. '0' AU When FEAT_THE is implemented 20 20 20 Reserved, RES0. Otherwise 19 19 19 Reserved, RES0. FNG1 18 18 0 Mask bit for FNG1. 0b0 TCR2_EL1.FNG1 is writable. 0b1 TCR2_EL1.FNG1 is not writable. '0' AU When FEAT_ASID2 is implemented 18 18 18 Reserved, RES0. Otherwise FNG0 17 17 0 Mask bit for FNG0. 0b0 TCR2_EL1.FNG0 is writable. 0b1 TCR2_EL1.FNG0 is not writable. '0' AU When FEAT_ASID2 is implemented 17 17 17 Reserved, RES0. Otherwise A2 16 16 0 Mask bit for A2. 0b0 TCR2_EL1.A2 is writable. 0b1 TCR2_EL1.A2 is not writable. '0' AU When FEAT_ASID2 is implemented 16 16 16 Reserved, RES0. Otherwise DisCH1 15 15 0 Mask bit for DisCH1. 0b0 TCR2_EL1.DisCH1 is writable. 0b1 TCR2_EL1.DisCH1 is not writable. '0' AU When FEAT_D128 is implemented 15 15 15 Reserved, RES0. Otherwise DisCH0 14 14 0 Mask bit for DisCH0. 0b0 TCR2_EL1.DisCH0 is writable. 0b1 TCR2_EL1.DisCH0 is not writable. '0' AU When FEAT_D128 is implemented 14 14 14 Reserved, RES0. Otherwise 13 12 13:12 Reserved, RES0. HAFT 11 11 0 Mask bit for HAFT. 0b0 TCR2_EL1.HAFT is writable. 0b1 TCR2_EL1.HAFT is not writable. '0' AU When FEAT_HAFT is implemented 11 11 11 Reserved, RES0. Otherwise PTTWI 10 10 0 Mask bit for PTTWI. 0b0 TCR2_EL1.PTTWI is writable. 0b1 TCR2_EL1.PTTWI is not writable. '0' AU When FEAT_THE is implemented 10 10 10 Reserved, RES0. Otherwise 9 6 9:6 Reserved, RES0. D128 5 5 0 Mask bit for D128. 0b0 TCR2_EL1.D128 is writable. 0b1 TCR2_EL1.D128 is not writable. '0' AU When FEAT_D128 is implemented 5 5 5 Reserved, RES0. Otherwise AIE 4 4 0 Mask bit for AIE. 0b0 TCR2_EL1.AIE is writable. 0b1 TCR2_EL1.AIE is not writable. '0' AU When FEAT_AIE is implemented 4 4 4 Reserved, RES0. Otherwise POE 3 3 0 Mask bit for POE. 0b0 TCR2_EL1.POE is writable. 0b1 TCR2_EL1.POE is not writable. '0' AU When FEAT_S1POE is implemented 3 3 3 Reserved, RES0. Otherwise E0POE 2 2 0 Mask bit for E0POE. 0b0 TCR2_EL1.E0POE is writable. 0b1 TCR2_EL1.E0POE is not writable. '0' AU When FEAT_S1POE is implemented 2 2 2 Reserved, RES0. Otherwise PIE 1 1 0 Mask bit for PIE. 0b0 TCR2_EL1.PIE is writable. 0b1 TCR2_EL1.PIE is not writable. '0' AU When FEAT_S1PIE is implemented 1 1 1 Reserved, RES0. Otherwise PnCH 0 0 0 Mask bit for PnCH. 0b0 TCR2_EL1.PnCH is writable. 0b1 TCR2_EL1.PnCH is not writable. '0' AU When FEAT_THE is implemented 0 0 0 Reserved, RES0. Otherwise When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TCR2MASK_EL1 or TCR2MASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, TCR2MASK_EL1 if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTCR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x338); else X{64}(t) = TCR2MASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCR2MASK_EL2(); else X{64}(t) = TCR2MASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCR2MASK_EL1(); end; MSR TCR2MASK_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nTCR2MASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x338) = X{64}(t); elsif !IsZero(TCR2MASK_EL1()) then Undefined(); else TCR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(TCR2MASK_EL2()) then Undefined(); else TCR2MASK_EL2() = X{64}(t); end; else TCR2MASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCR2MASK_EL1() = X{64}(t); end; MRS <Xt>, TCR2MASK_EL12 When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x338); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TCR2MASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = TCR2MASK_EL1(); else Undefined(); end; end; MSR TCR2MASK_EL12, <Xt> When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x338) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TCR2MASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TCR2MASK_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel