TCRMASK_EL1 Translation Control Masking Register (EL1) when FEAT_SRMASK is implemented and FEAT_AA64 is implemented Mask register to prevent updates of fields in TCR_EL1 on writes to TCR_EL1 or TCRALIAS_EL1. Other TCRMASK_EL1 is a 64-bit register. 63 62 63:62 Reserved, RES0. MTX1 61 61 0 Mask bit for MTX1. 0b0 TCR_EL1.MTX1 is writable. 0b1 TCR_EL1.MTX1 is not writable. '0' AU When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented 61 61 61 Reserved, RES0. Otherwise MTX0 60 60 0 Mask bit for MTX0. 0b0 TCR_EL1.MTX0 is writable. 0b1 TCR_EL1.MTX0 is not writable. '0' AU When FEAT_MTE_NO_ADDRESS_TAGS is implemented or FEAT_MTE_CANONICAL_TAGS is implemented 60 60 60 Reserved, RES0. Otherwise DS 59 59 0 Mask bit for DS. 0b0 TCR_EL1.DS is writable. 0b1 TCR_EL1.DS is not writable. '0' AU When FEAT_LPA2 is implemented 59 59 59 Reserved, RES0. Otherwise TCMA1 58 58 0 Mask bit for TCMA1. 0b0 TCR_EL1.TCMA1 is writable. 0b1 TCR_EL1.TCMA1 is not writable. '0' AU When FEAT_MTE2 is implemented 58 58 58 Reserved, RES0. Otherwise TCMA0 57 57 0 Mask bit for TCMA0. 0b0 TCR_EL1.TCMA0 is writable. 0b1 TCR_EL1.TCMA0 is not writable. '0' AU When FEAT_MTE2 is implemented 57 57 57 Reserved, RES0. Otherwise E0PD1 56 56 0 Mask bit for E0PD1. 0b0 TCR_EL1.E0PD1 is writable. 0b1 TCR_EL1.E0PD1 is not writable. '0' AU When FEAT_E0PD is implemented 56 56 56 Reserved, RES0. Otherwise E0PD0 55 55 0 Mask bit for E0PD0. 0b0 TCR_EL1.E0PD0 is writable. 0b1 TCR_EL1.E0PD0 is not writable. '0' AU When FEAT_E0PD is implemented 55 55 55 Reserved, RES0. Otherwise NFD1 54 54 0 Mask bit for NFD1. 0b0 TCR_EL1.NFD1 is writable. 0b1 TCR_EL1.NFD1 is not writable. '0' AU When FEAT_SVE is implemented 54 54 54 Reserved, RES0. Otherwise NFD0 53 53 0 Mask bit for NFD0. 0b0 TCR_EL1.NFD0 is writable. 0b1 TCR_EL1.NFD0 is not writable. '0' AU When FEAT_SVE is implemented 53 53 53 Reserved, RES0. Otherwise TBID1 52 52 0 Mask bit for TBID1. 0b0 TCR_EL1.TBID1 is writable. 0b1 TCR_EL1.TBID1 is not writable. '0' AU When FEAT_PAuth is implemented 52 52 52 Reserved, RES0. Otherwise TBID0 51 51 0 Mask bit for TBID0. 0b0 TCR_EL1.TBID0 is writable. 0b1 TCR_EL1.TBID0 is not writable. '0' AU When FEAT_PAuth is implemented 51 51 51 Reserved, RES0. Otherwise HWU162 50 50 0 Mask bit for HWU162. 0b0 TCR_EL1.HWU162 is writable. 0b1 TCR_EL1.HWU162 is not writable. '0' AU When FEAT_HPDS2 is implemented 50 50 50 Reserved, RES0. Otherwise HWU161 49 49 0 Mask bit for HWU161. 0b0 TCR_EL1.HWU161 is writable. 0b1 TCR_EL1.HWU161 is not writable. '0' AU When FEAT_HPDS2 is implemented 49 49 49 Reserved, RES0. Otherwise HWU160 48 48 0 Mask bit for HWU160. 0b0 TCR_EL1.HWU160 is writable. 0b1 TCR_EL1.HWU160 is not writable. '0' AU When FEAT_HPDS2 is implemented 48 48 48 Reserved, RES0. Otherwise HWU159 47 47 0 Mask bit for HWU159. 0b0 TCR_EL1.HWU159 is writable. 0b1 TCR_EL1.HWU159 is not writable. '0' AU When FEAT_HPDS2 is implemented 47 47 47 Reserved, RES0. Otherwise HWU062 46 46 0 Mask bit for HWU062. 0b0 TCR_EL1.HWU062 is writable. 0b1 TCR_EL1.HWU062 is not writable. '0' AU When FEAT_HPDS2 is implemented 46 46 46 Reserved, RES0. Otherwise HWU061 45 45 0 Mask bit for HWU061. 0b0 TCR_EL1.HWU061 is writable. 0b1 TCR_EL1.HWU061 is not writable. '0' AU When FEAT_HPDS2 is implemented 45 45 45 Reserved, RES0. Otherwise HWU060 44 44 0 Mask bit for HWU060. 0b0 TCR_EL1.HWU060 is writable. 0b1 TCR_EL1.HWU060 is not writable. '0' AU When FEAT_HPDS2 is implemented 44 44 44 Reserved, RES0. Otherwise HWU059 43 43 0 Mask bit for HWU059. 0b0 TCR_EL1.HWU059 is writable. 0b1 TCR_EL1.HWU059 is not writable. '0' AU When FEAT_HPDS2 is implemented 43 43 43 Reserved, RES0. Otherwise HPD1 42 42 0 Mask bit for HPD1. 0b0 TCR_EL1.HPD1 is writable. 0b1 TCR_EL1.HPD1 is not writable. '0' AU When FEAT_HPDS is implemented 42 42 42 Reserved, RES0. Otherwise HPD0 41 41 0 Mask bit for HPD0. 0b0 TCR_EL1.HPD0 is writable. 0b1 TCR_EL1.HPD0 is not writable. '0' AU When FEAT_HPDS is implemented 41 41 41 Reserved, RES0. Otherwise HD 40 40 0 Mask bit for HD. 0b0 TCR_EL1.HD is writable. 0b1 TCR_EL1.HD is not writable. '0' AU When FEAT_HAFDBS is implemented 40 40 40 Reserved, RES0. Otherwise HA 39 39 0 Mask bit for HA. 0b0 TCR_EL1.HA is writable. 0b1 TCR_EL1.HA is not writable. '0' AU When FEAT_HAF is implemented 39 39 39 Reserved, RES0. Otherwise TBI1 38 38 38 Mask bit for TBI1. 0b0 TCR_EL1.TBI1 is writable. 0b1 TCR_EL1.TBI1 is not writable. '0' AU TBI0 37 37 37 Mask bit for TBI0. 0b0 TCR_EL1.TBI0 is writable. 0b1 TCR_EL1.TBI0 is not writable. '0' AU AS 36 36 36 Mask bit for AS. 0b0 TCR_EL1.AS is writable. 0b1 TCR_EL1.AS is not writable. '0' AU 35 33 35:33 Reserved, RES0. IPS 32 32 32 Mask bit for IPS. 0b0 TCR_EL1.IPS is writable. 0b1 TCR_EL1.IPS is not writable. '0' AU 31 31 31 Reserved, RES0. TG1 30 30 30 Mask bit for TG1. 0b0 TCR_EL1.TG1 is writable. 0b1 TCR_EL1.TG1 is not writable. '0' AU 29 29 29 Reserved, RES0. SH1 28 28 28 Mask bit for SH1. 0b0 TCR_EL1.SH1 is writable. 0b1 TCR_EL1.SH1 is not writable. '0' AU 27 27 27 Reserved, RES0. ORGN1 26 26 26 Mask bit for ORGN1. 0b0 TCR_EL1.ORGN1 is writable. 0b1 TCR_EL1.ORGN1 is not writable. '0' AU 25 25 25 Reserved, RES0. IRGN1 24 24 24 Mask bit for IRGN1. 0b0 TCR_EL1.IRGN1 is writable. 0b1 TCR_EL1.IRGN1 is not writable. '0' AU EPD1 23 23 23 Mask bit for EPD1. 0b0 TCR_EL1.EPD1 is writable. 0b1 TCR_EL1.EPD1 is not writable. '0' AU A1 22 22 22 Mask bit for A1. 0b0 TCR_EL1.A1 is writable. 0b1 TCR_EL1.A1 is not writable. '0' AU 21 17 21:17 Reserved, RES0. T1SZ 16 16 16 Mask bit for T1SZ. 0b0 TCR_EL1.T1SZ is writable. 0b1 TCR_EL1.T1SZ is not writable. '0' AU 15 15 15 Reserved, RES0. TG0 14 14 14 Mask bit for TG0. 0b0 TCR_EL1.TG0 is writable. 0b1 TCR_EL1.TG0 is not writable. '0' AU 13 13 13 Reserved, RES0. SH0 12 12 12 Mask bit for SH0. 0b0 TCR_EL1.SH0 is writable. 0b1 TCR_EL1.SH0 is not writable. '0' AU 11 11 11 Reserved, RES0. ORGN0 10 10 10 Mask bit for ORGN0. 0b0 TCR_EL1.ORGN0 is writable. 0b1 TCR_EL1.ORGN0 is not writable. '0' AU 9 9 9 Reserved, RES0. IRGN0 8 8 8 Mask bit for IRGN0. 0b0 TCR_EL1.IRGN0 is writable. 0b1 TCR_EL1.IRGN0 is not writable. '0' AU EPD0 7 7 7 Mask bit for EPD0. 0b0 TCR_EL1.EPD0 is writable. 0b1 TCR_EL1.EPD0 is not writable. '0' AU 6 1 6:1 Reserved, RES0. T0SZ 0 0 0 Mask bit for T0SZ. 0b0 TCR_EL1.T0SZ is writable. 0b1 TCR_EL1.T0SZ is not writable. '0' AU When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name TCRMASK_EL1 or TCRMASK_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, TCRMASK_EL1 if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nTCRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x330); else X{64}(t) = TCRMASK_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = TCRMASK_EL2(); else X{64}(t) = TCRMASK_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TCRMASK_EL1(); end; MSR TCRMASK_EL1, <Xt> if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGWTR2_EL2().nTCRMASK_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2().SRMASKEn == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x330) = X{64}(t); elsif !IsZero(TCRMASK_EL1()) then Undefined(); else TCRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then if !IsZero(TCRMASK_EL2()) then Undefined(); else TCRMASK_EL2() = X{64}(t); end; else TCRMASK_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then TCRMASK_EL1() = X{64}(t); end; MRS <Xt>, TCRMASK_EL12 When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x330); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TCRMASK_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = TCRMASK_EL1(); else Undefined(); end; end; MSR TCRMASK_EL12, <Xt> When FEAT_VHE is implemented if !(IsFeatureImplemented(FEAT_SRMASK) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x330) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().SRMASKEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().SRMASKEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TCRMASK_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then TCRMASK_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel