TLBI ALLE1, TLBI ALLE1NXS TLB Invalidate All, EL1 when FEAT_AA64 is implemented Invalidates cached copies of translation table entries from TLBs that meet all the following requirements: The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk. If FEAT_RME is implemented, one of the following applies: SCR_EL3.{NSE, NS} is {0, 0} and the entry would be required to translate an address using the Secure EL1&0 translation regime. SCR_EL3.{NSE, NS} is {0, 1} and the entry would be required to translate an address using the Non-secure EL1&0 translation regime. SCR_EL3.{NSE, NS} is {1, 1} and the entry would be required to translate an address using the Realm EL1&0 translation regime. If FEAT_RME is not implemented, one of the following applies: SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL1&0 translation regime. SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL1&0 translation regime. The invalidation applies to entries with any VMID. The invalidation only applies to the PE that executes this System instruction. For the EL1&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID. If FEAT_XS is implemented, the nXS variant of this System instruction is defined. It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1. The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete. The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete. TLB TLBI ALLE1, TLBI ALLE1NXS is a 64-bit System instruction. The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether: The instruction is UNDEFINED. The instruction behaves as if the Rt field is set to 0b11111. This system instruction is an alias of the SYS instruction. The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBI_ALL() in the Pseudocode for AArch64 operation. TLBI ALLE1{, <Xt>} if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_AllAttr, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_AllAttr, X{64}(t)); end; end; TLBI ALLE1NXS{, <Xt>} When FEAT_XS is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_ExcludeXS, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_ALL(SecurityStateAtEL(EL1), Regime_EL10, Broadcast_NSH, TLBI_ExcludeXS, X{64}(t)); end; end; 2026-03-26 20:27:25 2026-03_rel