TLBI RVAE1IS, TLBI RVAE1ISNXS
TLB Range Invalidate by VA, EL1, Inner Shareable
when FEAT_TLBIRANGE is implemented and FEAT_AA64 is implemented
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 64-bit stage 1 translation table entry, from any level of the translation table walk up to the level indicated in the TTL hint.
If FEAT_D128 is implemented, a 128-bit stage 1 translation table entry, if TTL is 0b00.
The entry would be used to translate any of the VAs in the specified address range, and one of the following applies:
The entry is from a level of lookup above the final level and matches the specified ASID.
The entry is a global entry from the final level of lookup.
The entry is a non-global entry from the final level of lookup that matches the specified ASID.
The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].
When EL2 is implemented and enabled in the current Security state:
If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the entry would be used with the current VMID and would be required to translate any of the VAs in the specified address range using the EL1&0 translation regime for the Security state.
If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the entry would be required to translate any of the VAs in the specified address range using the EL2&0 translation regime for the Security state.
When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate any of the VAs in the specified address range using the EL1&0 translation regime for the Security state.
The Security state is indicated by the value of
SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
When
a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:A PE with SCR_EL3.EEL2==1 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==0.A PE with SCR_EL3.EEL2==0 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==1.A PE is architecturally required to invalidate all relevant entries in the Secure EL1&0 translation of a System MMU in the same required shareability domain with a VMID of 0.
For 64-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when:
For the 4K translation granule:
If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.
If TTL==10 and BaseADDR[20:12] is not equal to 000000000.
For the 16K translation granule:
If TTL==10 and BaseADDR[24:14] is not equal to 00000000000.
For the 64K translation granule:
If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.
If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.
The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
TLB
TLBI RVAE1IS, TLBI RVAE1ISNXS is a 64-bit System instruction.
ASID
63
48
63:48
ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.
Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field.
If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.
TG
47
46
47:46
Translation granule size.
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
0b00
Reserved.
0b01
4K translation granule.
0b10
16K translation granule.
0b11
64K translation granule.
SCALE
45
44
45:44
The exponent element of the calculation that is used to produce the upper range.
NUM
43
39
43:39
The base element of the calculation that is used to produce the upper range.
TTL
38
37
38:37
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
0b00
The entries in the range can be using any level for the translation table entries.
0b01
The TTL hint indicates level 1.
If FEAT_LPA2 is not implemented, when using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00.
0b10
The TTL hint indicates level 2.
0b11
The TTL hint indicates level 3.
BaseADDR
36
0
36:0
The starting address for the range of the maintenance instructions. This field is BaseADDR[52:16] for all translation granules.
When using a 4KB translation granule, BaseADDR[15:12] is treated as 0b0000.
When using a 16KB translation granule, BaseADDR[15:14] is treated as 0b00.
When (FEAT_LPA2 is implemented and TCR_EL1.DS == '1') or (FEAT_D128 is implemented and TCR2_EL1.D128 == '1')
BaseADDR
36
0
36:0
The starting address for the range of the maintenance instruction.
When using a 4KB translation granule, this field is BaseADDR[48:12].
When using a 16KB translation granule, this field is BaseADDR[50:14].
When using a 64KB translation granule, this field is BaseADDR[52:16].
Otherwise
This system instruction is an alias of the SYS instruction.
The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBI_RVA() in the Pseudocode for AArch64 operation.
TLBI RVAE1IS{, <Xt>}
if !(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBIS == '1') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().TLBIRVAE1IS == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_TLBI_RVA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Any, TLBI_AllAttr, X{64}(t));
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBI_RVA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Any, TLBI_AllAttr, X{64}(t));
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then
return;
else
AArch64_TLBI_RVA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Any, TLBI_AllAttr, X{64}(t));
end;
end;
TLBI RVAE1ISNXS{, <Xt>}
When FEAT_XS is implemented
if !(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif !IsFeatureImplemented(FEAT_XS) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBIS == '1') then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_HCX) && (!IsHCRXEL2Enabled() || HCRX_EL2().FGTnXS == '0') && HFGITR_EL2().TLBIRVAE1IS == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
else
AArch64_TLBI_RVA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Any, TLBI_ExcludeXS, X{64}(t));
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBI_RVA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Any, TLBI_ExcludeXS, X{64}(t));
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then
return;
else
AArch64_TLBI_RVA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Any, TLBI_ExcludeXS, X{64}(t));
end;
end;
2026-03-26 20:27:25
2026-03_rel