TLBI RVALE3OS, TLBI RVALE3OSNXS
TLB Range Invalidate by VA, Last level, EL3, Outer Shareable
when FEAT_TLBIRANGE is implemented, FEAT_TLBIOS is implemented, and FEAT_AA64 is implemented
If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 64-bit stage 1 translation table entry, from the final level of the translation table walk up to the level indicated in the TTL hint.
If FEAT_D128 is implemented, a 128-bit stage 1 translation table entry, if TTL is 0b00.
The entry would be used to translate any of the VAs in the specified address range using the EL3 translation regime.
The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].
The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.
For 64-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when:
For the 4K translation granule:
If TTL==01 and BaseADDR[29:12] is not equal to 000000000000000000.
If TTL==10 and BaseADDR[20:12] is not equal to 000000000.
For the 16K translation granule:
If TTL==10 and BaseADDR[24:14] is not equal to 00000000000.
For the 64K translation granule:
If TTL==01 and BaseADDR[41:16] is not equal to 00000000000000000000000000.
If TTL==10 and BaseADDR[28:16] is not equal to 0000000000000.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.
The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
TLB
TLBI RVALE3OS, TLBI RVALE3OSNXS is a 64-bit System instruction.
63
48
63:48
Reserved, RES0.
TG
47
46
47:46
Translation granule size.
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
0b00
Reserved.
0b01
4K translation granule.
0b10
16K translation granule.
0b11
64K translation granule.
SCALE
45
44
45:44
The exponent element of the calculation that is used to produce the upper range.
NUM
43
39
43:39
The base element of the calculation that is used to produce the upper range.
TTL
38
37
38:37
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
0b00
The entries in the range can be using any level for the translation table entries.
0b01
The TTL hint indicates level 1.
If FEAT_LPA2 is not implemented, when using a 16KB translation granule, this value is reserved and hardware should treat this field as 0b00.
0b10
The TTL hint indicates level 2.
0b11
The TTL hint indicates level 3.
BaseADDR
36
0
36:0
The starting address for the range of the maintenance instructions. This field is BaseADDR[52:16] for all translation granules.
When using a 4KB translation granule, BaseADDR[15:12] is treated as 0b0000.
When using a 16KB translation granule, BaseADDR[15:14] is treated as 0b00.
When (FEAT_LPA2 is implemented and TCR_EL3.DS == '1') or (FEAT_D128 is implemented and TCR_EL3.D128 == '1')
BaseADDR
36
0
36:0
The starting address for the range of the maintenance instruction.
When using a 4KB translation granule, this field is BaseADDR[48:12].
When using a 16KB translation granule, this field is BaseADDR[50:14].
When using a 64KB translation granule, this field is BaseADDR[52:16].
Otherwise
This system instruction is an alias of the SYS instruction.
TLBI RVALE3OS{, <Xt>}
if !(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3) then
return;
else
AArch64_TLBI_RVA(SecurityStateAtEL(EL3), Regime_EL3, VMID_NONE, Broadcast_OSH, TLBILevel_Last, TLBI_AllAttr, X{64}(t));
end;
end;
TLBI RVALE3OSNXS{, <Xt>}
When FEAT_XS is implemented
if !(IsFeatureImplemented(FEAT_TLBIRANGE) && IsFeatureImplemented(FEAT_TLBIOS) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif !IsFeatureImplemented(FEAT_XS) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3) then
return;
else
AArch64_TLBI_RVA(SecurityStateAtEL(EL3), Regime_EL3, VMID_NONE, Broadcast_OSH, TLBILevel_Last, TLBI_ExcludeXS, X{64}(t));
end;
end;
2026-03-26 20:27:25
2026-03_rel