TLBI VAALE1, TLBI VAALE1NXS TLB Invalidate by VA, All ASID, Last level, EL1 when FEAT_AA64 is implemented Invalidates cached copies of translation table entries from TLBs that meet all the following requirements: The entry is one of the following: A 64-bit stage 1 translation table entry, from the final level of the translation table walk. If FEAT_D128 is implemented, a 128-bit stage 1 translation table entry, from the final level of the translation table walk, if TTL[3:2] is 0b00. When EL2 is implemented and enabled in the current Security state: If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the entry would be used with the current VMID and would be required to translate the specified VA using the EL1&0 translation regime for the Security state. If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the entry would be required to translate the specified VA using the EL2&0 translation regime for the Security state. When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime for the Security state. The Security state is indicated by the value of SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented. The invalidation applies to the PE that executes this System instruction. For the EL1&0 and EL2&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID. If FEAT_XS is implemented, the nXS variant of this System instruction is defined. It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1. The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete. The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete. TLB TLBI VAALE1, TLBI VAALE1NXS is a 64-bit System instruction. 63 48 63:48 Reserved, RES0. TTL 47 44 3:0 Translation Table Level. Indicates the level of the translation table walk that holds the leaf entry for the address being invalidated. If an incorrect value of the TTL field is specified for the entry being invalidated by the instruction, then no entries are required by the architecture to be invalidated from the TLB. 0b00xx No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0. 0b01xx The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : If FEAT_LPA2 is implemented, level 0. Otherwise, treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. 0b10xx The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : If FEAT_LPA2 is implemented, level 1. Otherwise, treat as if TTL<3:2> is 0b00. 0b10 : Level 2. 0b11 : Level 3. 0b11xx The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. When FEAT_TTL is implemented 47 44 47:44 Reserved, RES0. Otherwise VA[55:12] 43 0 43:0 Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the VA will be affected by this System instruction, regardless of the ASID. If the TLB maintenance instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then the software must treat bits[55:32] as RES0. The treatment of the low-order bits of this field depends on the translation granule size, as follows: Where a 4KB translation granule is being used, all bits are valid and used for the invalidation. Where a 16KB translation granule is being used, bits [1:0] of this field are RES0 and ignored when the instruction is executed, because VA[13:12] have no effect on the operation of the instruction. Where a 64KB translation granule is being used, bits [3:0] of this field are RES0 and ignored when the instruction is executed, because VA[15:12] have no effect on the operation of the instruction. This system instruction is an alias of the SYS instruction. The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBI_VAA() in the Pseudocode for AArch64 operation. TLBI VAALE1{, <Xt>} if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TTLB == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().TLBIVAALE1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Last, TLBI_AllAttr, X{64}(t)); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Last, TLBI_AllAttr, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Last, TLBI_AllAttr, X{64}(t)); end; end; TLBI VAALE1NXS{, <Xt>} When FEAT_XS is implemented if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TTLB == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_HCX) && (!IsHCRXEL2Enabled() || HCRX_EL2().FGTnXS == '0') && HFGITR_EL2().TLBIVAALE1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Last, TLBI_ExcludeXS, X{64}(t)); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Last, TLBI_ExcludeXS, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Last, TLBI_ExcludeXS, X{64}(t)); end; end; 2026-03-26 20:27:25 2026-03_rel