TLBI VMALLE1OS, TLBI VMALLE1OSNXS TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable when FEAT_TLBIOS is implemented and FEAT_AA64 is implemented Invalidates cached copies of translation table entries from TLBs that meet all the following requirements: The entry is a stage 1 translation table entry, from any level of the translation table walk. When EL2 is implemented and enabled in the current Security state: If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the entry would be used with the current VMID and would be required to translate the specified VA using the EL1&0 translation regime for the Security state. If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the entry would be required to translate the specified VA using the EL2&0 translation regime for the Security state. When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime for the Security state. The Security state is indicated by the value of SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented. The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction. When a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:A PE with SCR_EL3.EEL2==1 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==0.A PE with SCR_EL3.EEL2==0 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==1.A PE is architecturally required to invalidate all relevant entries in the Secure EL1&0 translation of a System MMU in the same required shareability domain with a VMID of 0. For the EL1&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID. If FEAT_XS is implemented, the nXS variant of this System instruction is defined. It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1. The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete. The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete. TLB TLBI VMALLE1OS, TLBI VMALLE1OSNXS is a 64-bit System instruction. The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether: The instruction is UNDEFINED. The instruction behaves as if the Rt field is set to 0b11111. This system instruction is an alias of the SYS instruction. The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBI_VMALL() in the Pseudocode for AArch64 operation. TLBI VMALLE1OS{, <Xt>} if !(IsFeatureImplemented(FEAT_TLBIOS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBOS == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().TLBIVMALLE1OS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_AllAttr, X{64}(t)); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_AllAttr, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_AllAttr, X{64}(t)); end; end; TLBI VMALLE1OSNXS{, <Xt>} When FEAT_XS is implemented if !(IsFeatureImplemented(FEAT_TLBIOS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBOS == '1') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_HCX) && (!IsHCRXEL2Enabled() || HCRX_EL2().FGTnXS == '0') && HFGITR_EL2().TLBIVMALLE1OS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_ExcludeXS, X{64}(t)); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_ExcludeXS, X{64}(t)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBI_ExcludeXS, X{64}(t)); end; end; 2026-03-26 20:27:25 2026-03_rel