TLBIP RIPAS2E1OS, TLBIP RIPAS2E1OSNXS
TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable
when FEAT_D128 is implemented and FEAT_AA64 is implemented
If EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 128-bit stage 2 only translation table entry, from any level of the translation table walk up to the level indicated in the TTL hint.
A 64-bit stage 2 only translation table entry, from any level of the translation table walk, if TTL is 0b00.
If FEAT_RME is implemented, one of the following applies:
SCR_EL3.{NSE, NS} is {0, 0} and the entry would be required to translate any IPA in the specified address range using the Secure EL1&0 translation regime.
SCR_EL3.{NSE, NS} is {0, 1} and the entry would be required to translate any IPA in the specified address range using the Non-secure EL1&0 translation regime.
SCR_EL3.{NSE, NS} is {1, 1} and the entry would be required to translate any IPA in the specified address range using the Realm EL1&0 translation regime.
If FEAT_RME is not implemented, one of the following applies:
SCR_EL3.NS is 0 and the entry would be required to translate any IPA in the specified address range using the Secure EL1&0 translation regime.
SCR_EL3.NS is 1 and the entry would be required to translate any IPA in the specified address range using the Non-secure EL1&0 translation regime.
The entry would be used with the current VMID.
The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].
The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.
The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.
For 128-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for the translation system is not aligned.
For more information about the architectural requirements for this System instruction, see 'Invalidating TLB entries from stage 2 translations'.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.
The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
TLB
Virt
TLBIP RIPAS2E1OS, TLBIP RIPAS2E1OSNXS is a 128-bit System instruction.
127
108
127:108
Reserved, RES0.
BaseADDR[55:12]
107
64
107:64
The starting address for the range of the maintenance instructions. This field is BaseADDR[55:12] for all translation granules.
NS
63
63
0
When the instruction is executed and SCR_EL3.{NSE, NS} == {0, 0}, NS selects the IPA space.
When the instruction is executed and SCR_EL3.{NSE, NS} == {1, 1}, this field is RES0, and the instruction applies only to the Realm IPA space.
When the instruction is executed and SCR_EL3.{NSE, NS} == {0, 1}, this field is RES0, and the instruction applies only to the Non-secure IPA space.
0b0
IPA is in the Secure IPA space.
0b1
IPA is in the Non-secure IPA space.
When FEAT_RME is implemented
NS
63
63
0
Not Secure. Specifies the IPA space.
When the instruction is executed in Non-secure state, this field is RES0, and the instruction applies only to the Non-secure IPA space.
When FEAT_SEL2 is not implemented, or if EL2 is disabled in the current Security state, this field is RES0.
0b0
IPA is in the Secure IPA space.
0b1
IPA is in the Non-secure IPA space.
When FEAT_SEL2 is implemented and FEAT_RME is not implemented
63
63
63
Reserved, RES0.
Otherwise
62
48
62:48
Reserved, RES0.
TG
47
46
47:46
Translation granule size.
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
0b00
Reserved.
0b01
4K translation granule.
0b10
16K translation granule.
0b11
64K translation granule.
SCALE
45
44
45:44
The exponent element of the calculation that is used to produce the upper range.
NUM
43
39
43:39
The base element of the calculation that is used to produce the upper range.
TTL
38
37
38:37
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
0b00
The entries in the range can be using any level for the translation table entries.
0b01
The TTL hint indicates level 1.
0b10
The TTL hint indicates level 2.
0b11
The TTL hint indicates level 3.
36
0
36:0
Reserved, RES0.
This system instruction is an alias of the SYSP instruction.
TLBIP RIPAS2E1OS{, <Xt>, <Xt2>}
if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x14);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Any, TLBI_AllAttr, X{128}(t, t2));
elsif PSTATE.EL == EL3 then
if !EL2Enabled() then
return;
else
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then
return;
else
AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Any, TLBI_AllAttr, X{128}(t, t2));
end;
end;
end;
TLBIP RIPAS2E1OSNXS{, <Xt>, <Xt2>}
if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif !IsFeatureImplemented(FEAT_XS) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x14);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Any, TLBI_ExcludeXS, X{128}(t, t2));
elsif PSTATE.EL == EL3 then
if !EL2Enabled() then
return;
else
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then
return;
else
AArch64_TLBIP_RIPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Any, TLBI_ExcludeXS, X{128}(t, t2));
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel