TLBIP RVAALE1OS, TLBIP RVAALE1OSNXS
TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable
when FEAT_D128 is implemented and FEAT_AA64 is implemented
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 128-bit stage 1 translation table entry, from the leaf level of the translation table walk, indicated by the TTL hint.
A 64-bit stage 1 translation table entry, from the leaf level of the translation table walk, if TTL is 0b00.
The entry is within the address range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)].
When EL2 is implemented and enabled in the current Security state:
If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the entry would be used with the current VMID and would be required to translate any of the VAs in the specified address range using the EL1&0 translation regime for the Security state.
If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the entry would be required to translate any of the VAs in the specified address range using the EL2&0 translation regime for the Security state.
When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate any of the VAs in the specified address range using the EL1&0 translation regime for the Security state.
The Security state is indicated by the value of
SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.
The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction.
When
a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:A PE with SCR_EL3.EEL2==1 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==0.A PE with SCR_EL3.EEL2==0 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==1.A PE is architecturally required to invalidate all relevant entries in the Secure EL1&0 translation of a System MMU in the same required shareability domain with a VMID of 0.
For the EL1&0 and EL2&0 translation regimes, the invalidation applies to both global entries and non-global entries with any ASID.
For 128-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for the translation system is not aligned.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.
The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
TLB
TLBIP RVAALE1OS, TLBIP RVAALE1OSNXS is a 128-bit System instruction.
127
108
127:108
Reserved, RES0.
BaseADDR[55:12]
107
64
107:64
The starting address for the range of the maintenance instructions. This field is BaseADDR[55:12] for all translation granules.
63
48
63:48
Reserved, RES0.
TG
47
46
47:46
Translation granule size.
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
0b00
Reserved.
0b01
4K translation granule.
0b10
16K translation granule.
0b11
64K translation granule.
SCALE
45
44
45:44
The exponent element of the calculation that is used to produce the upper range.
NUM
43
39
43:39
The base element of the calculation that is used to produce the upper range.
TTL
38
37
38:37
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
0b00
The entries in the range can be using any level for the translation table entries.
0b01
The TTL hint indicates level 1.
0b10
The TTL hint indicates level 2.
0b11
The TTL hint indicates level 3.
36
0
36:0
Reserved, RES0.
This system instruction is an alias of the SYSP instruction.
The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBIP_RVAA() in the Pseudocode for AArch64 operation.
TLBIP RVAALE1OS{, <Xt>, <Xt2>}
if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBOS == '1') then
AArch64_SystemAccessTrap(EL2, 0x14);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().TLBIRVAALE1OS == '1' then
AArch64_SystemAccessTrap(EL2, 0x14);
else
AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Last, TLBI_AllAttr, X{128}(t, t2));
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Last, TLBI_AllAttr, X{128}(t, t2));
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then
return;
else
AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Last, TLBI_AllAttr, X{128}(t, t2));
end;
end;
TLBIP RVAALE1OSNXS{, <Xt>, <Xt2>}
if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif !IsFeatureImplemented(FEAT_XS) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBOS == '1') then
AArch64_SystemAccessTrap(EL2, 0x14);
elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_HCX) && (!IsHCRXEL2Enabled() || HCRX_EL2().FGTnXS == '0') && HFGITR_EL2().TLBIRVAALE1OS == '1' then
AArch64_SystemAccessTrap(EL2, 0x14);
else
AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Last, TLBI_ExcludeXS, X{128}(t, t2));
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Last, TLBI_ExcludeXS, X{128}(t, t2));
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then
return;
else
AArch64_TLBIP_RVAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_OSH, TLBILevel_Last, TLBI_ExcludeXS, X{128}(t, t2));
end;
end;
2026-03-26 20:27:25
2026-03_rel