TLBIP RVAE2, TLBIP RVAE2NXS
TLB Range Invalidate by VA, EL2
when FEAT_D128 is implemented and FEAT_AA64 is implemented
When EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 128-bit stage 1 translation table entry, from any level of the translation table walk up to the level indicated in the TTL hint.
A 64-bit stage 1 translation table entry, if TTL is 0b00.
The entry would be used to translate any VA
in the range determined by the formula [BaseADDR <= VA < BaseADDR + ((NUM +1)*2(5*SCALE +1) * Translation_Granule_Size)]
using the EL2 or EL2&0 translation regime, as determined by the Effective value of HCR_EL2.E2H, for the Security state.
If the Effective value of HCR_EL2.E2H is not 1, the entry is from any level of the translation table walk.
If the Effective value of HCR_EL2.E2H is 1, one of the following applies:
The entry is from a level of the translation table walk above the final level and matches the specified ASID.
The entry is a global entry from the final level of the translation table walk.
The entry is a non-global entry from the final level of the translation table walk that matches the specified ASID.
The Security state is indicated by the value of
SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented.
The invalidation applies to the PE that executes this System instruction.
For 128-bit translation table entry, the range of addresses invalidated is UNPREDICTABLE when Block or Page size corresponding to TTL and TG, for the translation system is not aligned.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.
The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
TLB
TLBIP RVAE2, TLBIP RVAE2NXS is a 128-bit System instruction.
127
108
127:108
Reserved, RES0.
BaseADDR[55:12]
107
64
107:64
The starting address for the range of the maintenance instructions. This field is BaseADDR[55:12] for all translation granules.
ASID
63
48
15:0
ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.
Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field.
If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits.
When ELIsInHost(EL2)
63
48
63:48
Reserved, RES0.
Otherwise
TG
47
46
47:46
Translation granule size.
The instruction takes a translation granule size for the translations that are being invalidated. If the translations used a different translation granule size than the one being specified, then the architecture does not require that the instruction invalidates any entries.
0b00
Reserved.
0b01
4K translation granule.
0b10
16K translation granule.
0b11
64K translation granule.
SCALE
45
44
45:44
The exponent element of the calculation that is used to produce the upper range.
NUM
43
39
43:39
The base element of the calculation that is used to produce the upper range.
TTL
38
37
38:37
TTL Level hint. The TTL hint is only guaranteed to invalidate:
Non-leaf-level entries in the range up to but not including the level described by the TTL hint.
Leaf-level entries in the range that match the level described by the TTL hint.
0b00
The entries in the range can be using any level for the translation table entries.
0b01
The TTL hint indicates level 1.
0b10
The TTL hint indicates level 2.
0b11
The TTL hint indicates level 3.
36
0
36:0
Reserved, RES0.
This system instruction is an alias of the SYSP instruction.
The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBIP_RVA() in the Pseudocode for AArch64 operation.
TLBIP RVAE2{, <Xt>, <Xt2>}
if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x14);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, X{128}(t, t2));
elsif PSTATE.EL == EL3 then
if !EL2Enabled() then
Undefined();
else
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2) then
return;
else
AArch64_TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, X{128}(t, t2));
end;
end;
end;
TLBIP RVAE2NXS{, <Xt>, <Xt2>}
if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif !IsFeatureImplemented(FEAT_XS) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EffectiveHCR_EL2_NVx() IN {'xx1'} then
AArch64_SystemAccessTrap(EL2, 0x14);
else
Undefined();
end;
elsif PSTATE.EL == EL2 then
AArch64_TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_ExcludeXS, X{128}(t, t2));
elsif PSTATE.EL == EL3 then
if !EL2Enabled() then
Undefined();
else
if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL2) then
return;
else
AArch64_TLBIP_RVA(SecurityStateAtEL(EL2), Regime_EL2, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_ExcludeXS, X{128}(t, t2));
end;
end;
end;
2026-03-26 20:27:25
2026-03_rel