TLBIP VAE3OS, TLBIP VAE3OSNXS TLB Invalidate Pair by VA, EL3, Outer Shareable when FEAT_D128 is implemented and FEAT_AA64 is implemented If EL3 is implemented, invalidates cached copies of translation table entries from TLBs that meet all the following requirements: The entry is one of the following: A 128-bit stage 1 translation table entry, from any level of the translation table walk. A 64-bit stage 1 translation table entry, from any level of the translation table walk, if TTL[3:2] is 0b00. The entry would be used to translate the specified VA using the EL3 translation regime. The invalidation applies to all PEs in the same Outer Shareable shareability domain as the PE that executes this System instruction. If FEAT_XS is implemented, the nXS variant of this System instruction is defined. It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1. The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete. The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete. TLB TLBIP VAE3OS, TLBIP VAE3OSNXS is a 128-bit System instruction. 127 108 127:108 Reserved, RES0. VA[55:12] 107 64 107:64 Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the ASID value (if appropriate) and VA will be affected by this System instruction. The treatment of the low-order bits of this field depends on the translation granule size, as follows: Where a 4KB translation granule is being used, all bits are valid and used for the invalidation. Where a 16KB translation granule is being used, bits [1:0] of this field are RES0 and ignored when the instruction is executed, because VA[13:12] have no effect on the operation of the instruction. Where a 64KB translation granule is being used, bits [3:0] of this field are RES0 and ignored when the instruction is executed, because VA[15:12] have no effect on the operation of the instruction. 63 48 63:48 Reserved, RES0. TTL 47 44 3:0 Translation Table Level. Indicates the level of the translation table walk that holds the leaf entry for the address being invalidated. If an incorrect value of the TTL field is specified for the entry being invalidated by the instruction, then no entries are required by the architecture to be invalidated from the TLB. 0b00xx No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0. 0b01xx The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Level 0. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. 0b10xx The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. 0b11xx The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. When FEAT_TTL is implemented 47 44 47:44 Reserved, RES0. Otherwise 43 0 43:0 Reserved, RES0. This system instruction is an alias of the SYSP instruction. TLBIP VAE3OS{, <Xt>, <Xt2>} if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3) then return; else AArch64_TLBIP_VA(SecurityStateAtEL(EL3), Regime_EL3, VMID_NONE, Broadcast_OSH, TLBILevel_Any, TLBI_AllAttr, X{128}(t, t2)); end; end; TLBIP VAE3OSNXS{, <Xt>, <Xt2>} if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL3) then return; else AArch64_TLBIP_VA(SecurityStateAtEL(EL3), Regime_EL3, VMID_NONE, Broadcast_OSH, TLBILevel_Any, TLBI_ExcludeXS, X{128}(t, t2)); end; end; 2026-03-26 20:27:25 2026-03_rel