TLBIP VALE1IS, TLBIP VALE1ISNXS TLB Invalidate Pair by VA, Last level, EL1, Inner Shareable when FEAT_D128 is implemented and FEAT_AA64 is implemented Invalidates cached copies of translation table entries from TLBs that meet all the following requirements: The entry is one of the following: A 128-bit stage 1 translation table entry. A 64-bit stage 1 translation table entry, if TTL[3:2] is 0b00. The entry would be used to translate the specified VA, and one of the following applies: The entry is a global entry from the final level of lookup. The entry is a non-global entry from the final level of lookup that matches the specified ASID. When EL2 is implemented and enabled in the current Security state: If the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, the entry would be used with the current VMID and would be required to translate the specified VA using the EL1&0 translation regime for the Security state. If the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, the entry would be required to translate the specified VA using the EL2&0 translation regime for the Security state. When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime for the Security state. The Security state is indicated by the value of SCR_EL3.NS if FEAT_RME is not implemented, or SCR_EL3.{NSE, NS} if FEAT_RME is implemented. The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction. From Armv8.4, when a TLB maintenance instruction is generated to the Secure EL1&0 translation regime and is defined to pass a VMID argument, or would be defined to pass a VMID argument if SCR_EL3.EEL2==1, then:A PE with SCR_EL3.EEL2==1 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==0.A PE with SCR_EL3.EEL2==0 is not architecturally required to invalidate any entries in the Secure EL1&0 translation of a PE in the same required shareability domain with SCR_EL3.EEL2==1.A PE is architecturally required to invalidate all relevant entries in the Secure EL1&0 translation of a System MMU in the same required shareability domain with a VMID of 0. If FEAT_XS is implemented, the nXS variant of this System instruction is defined. It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1. The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete. The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete. TLB TLBIP VALE1IS, TLBIP VALE1ISNXS is a 128-bit System instruction. 127 108 127:108 Reserved, RES0. VA[55:12] 107 64 107:64 Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the ASID value (if appropriate) and VA will be affected by this System instruction. The treatment of the low-order bits of this field depends on the translation granule size, as follows: Where a 4KB translation granule is being used, all bits are valid and used for the invalidation. Where a 16KB translation granule is being used, bits [1:0] of this field are RES0 and ignored when the instruction is executed, because VA[13:12] have no effect on the operation of the instruction. Where a 64KB translation granule is being used, bits [3:0] of this field are RES0 and ignored when the instruction is executed, because VA[15:12] have no effect on the operation of the instruction. ASID 63 48 63:48 ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction. Global TLB entries that match the VA value will be affected by this System instruction, regardless of the value of the ASID field. If the implementation supports 16 bits of ASID, then the upper 8 bits of the ASID must be written to 0 by software when the context being invalidated only uses 8 bits. TTL 47 44 3:0 Translation Table Level. Indicates the level of the translation table walk that holds the leaf entry for the address being invalidated. If an incorrect value of the TTL field is specified for the entry being invalidated by the instruction, then no entries are required by the architecture to be invalidated from the TLB. 0b00xx No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0. 0b01xx The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Level 0. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. 0b10xx The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. 0b11xx The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. When FEAT_TTL is implemented 47 44 47:44 Reserved, RES0. Otherwise 43 0 43:0 Reserved, RES0. This system instruction is an alias of the SYSP instruction. The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_TLBIP_VA() in the Pseudocode for AArch64 operation. TLBIP VALE1IS{, <Xt>, <Xt2>} if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBIS == '1') then AArch64_SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().TLBIVALE1IS == '1' then AArch64_SystemAccessTrap(EL2, 0x14); else AArch64_TLBIP_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_AllAttr, X{128}(t, t2)); end; elsif PSTATE.EL == EL2 then AArch64_TLBIP_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_AllAttr, X{128}(t, t2)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBIP_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_AllAttr, X{128}(t, t2)); end; end; TLBIP VALE1ISNXS{, <Xt>, <Xt2>} if !(IsFeatureImplemented(FEAT_D128) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().TTLB == '1' || HCR_EL2().TTLBIS == '1') then AArch64_SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_HCX) && (!IsHCRXEL2Enabled() || HCRX_EL2().FGTnXS == '0') && HFGITR_EL2().TLBIVALE1IS == '1' then AArch64_SystemAccessTrap(EL2, 0x14); else AArch64_TLBIP_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_ExcludeXS, X{128}(t, t2)); end; elsif PSTATE.EL == EL2 then AArch64_TLBIP_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_ExcludeXS, X{128}(t, t2)); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBIP_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_ExcludeXS, X{128}(t, t2)); end; end; 2026-03-26 20:27:25 2026-03_rel