TPIDR_EL0 EL0 Read/Write Software Thread ID Register when FEAT_AA64 is implemented TPIDRURW Architectural AArch32 31 0 31 0 31 0 31 0 Provides a location where software executing at EL0 can store thread identifying information, for OS management purposes. The PE makes no use of this register. Thread TPIDR_EL0 is a 64-bit register. ThreadID Thread ID 63 0 63:0 Thread ID. Thread identifying information stored by software running at this Exception level. AU MRS <Xt>, TPIDR_EL0 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().TPIDR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = TPIDR_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().TPIDR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = TPIDR_EL0(); end; elsif PSTATE.EL == EL2 then X{64}(t) = TPIDR_EL0(); elsif PSTATE.EL == EL3 then X{64}(t) = TPIDR_EL0(); end; MSR TPIDR_EL0, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().TPIDR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else TPIDR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().TPIDR_EL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else TPIDR_EL0() = X{64}(t); end; elsif PSTATE.EL == EL2 then TPIDR_EL0() = X{64}(t); elsif PSTATE.EL == EL3 then TPIDR_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel