TRBIDR_EL1
Trace Buffer ID Register
when FEAT_TRBE is implemented
TRBIDR_EL1
Architectural
External
63
0
63
0
63
0
63
0
when FEAT_TRBE_EXT is implemented
Describes constraints on using the Trace Buffer Unit to software, including whether the Trace Buffer Unit can be programmed at the current Exception level.
Identification Registers
TRBIDR_EL1 is a 64-bit register.
63
48
63:48
Reserved, RES0.
MaxBuffSize
47
32
47:32
Maximum supported trace buffer size. Reserved for software use.
The only permitted value is 0x0000, indicating there is no limit to the maximum buffer size.
Permitted values relate to the values an implementation is permitted to set this field to. A hypervisor might trap accesses to this register and use other values to describe limitations of its virtualization support to a guest operating system, as follows:MaxBuffSize bits[8:0] encodes a mantissa value, M.MaxBuffSize bits[13:9] encodes an exponent value, E.MaxBuffSize bits[15:14] are reserved.
The maximum buffer size, in bytes, is expressed using the following function: if IsZero(E), then UInt(M:Zeros(12)) else UInt('1':M:Zeros(UInt(E)+11)) For example:A value of 0x0001 means a maximum buffer size of 4KB.A value of 0x3FFF means a maximum buffer size of 4092TB.
Reads as 0x0000.
RO
31
16
31:16
Reserved, RES0.
MPAM
15
12
3:0
FEAT_MPAMv0p1 or FEAT_MPAMv1p0 extensions. Indicates Memory Partitioning and Monitoring (MPAM) support in the Trace Buffer Unit when using External mode.
When FEAT_MPAMv0p1 and FEAT_MPAMv1p0 are not implemented by the PE, the only permitted value is 0b0000.
When either FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented by the PE, the value 0b0000 is not permitted.
FEAT_TRBE_MPAM implements the functionality identified by the value 0b0010.
0b0000
FEAT_MPAMv0p1 and FEAT_MPAMv1p0 are not implemented by the PE.
0b0001
FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented by the Trace Buffer Unit, using Default physical PARTID and PMG values in External mode.
0b0010
Trace Buffer MPAM extensions implemented, using FEAT_MPAMv0p1 or FEAT_MPAMv1p0.
RO
When FEAT_TRBE_EXT is implemented
15
12
15:12
Reserved, RES0.
Otherwise
EA
11
8
11:8
External Abort handling. Describes how the PE manages External aborts on writes made by the Trace Buffer Unit to the trace buffer.
All other values are reserved.
From Armv9.3, the value 0b0000 is not permitted.
The behavior described by this field does not apply for External aborts on a translation table walk, translation table update, or GPT walk made by the Trace Buffer Unit that are reported as MMU faults using TRBSR_ELx. For more information, see 'External aborts'.
0b0000
Not described.
0b0001
The PE ignores External aborts on writes made by the Trace Buffer Unit.
0b0010
An External abort on a write made by the Trace Buffer Unit generates an asynchronous SError exception at the PE.
RO
AddrMode
7
6
7:6
Address Modes. Describes the addressing modes available for the trace buffer.
Other values are reserved.
If the Effective value of TRFCR_EL2.DnVM is 1 and the value returned for TRBIDR_EL1.P is 0, then this field reads as 0b01. Otherwise, this field reads as 0b00.
A hypervisor might trap accesses to this register to describe limitations of its virtualization support to a guest operating system.
0b00
Virtual and physical address modes are supported.
0b01
Only virtual address mode is supported.
0b10
Reserved for software use under virtualization, to show that only physical address mode is supported.
F
5
5
5
Flag updates. Describes how address translations performed by the Trace Buffer Unit manage the Access flag and dirty state.
If hardware management of the Access flag is disabled for a stage of translation, an access to a Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.
If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor and might generate a Permission fault, depending on the values of the access permission bits in the descriptor.
From Armv9.3, the value 0 is not permitted.
0b0
Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is always disabled for all translation stages.
0b1
Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is controlled in the same way as explicit memory accesses in the trace buffer owning translation regime.
RO
P
4
4
4
Programming not allowed. When read at EL3, this field reads as zero. Otherwise, indicates that the trace buffer owning Exception level is a higher Exception level or the trace buffer owning Security state is not the current Security state.
The value read from this field depends on the current Exception level and the Effective values of
MDCR_EL3.NSTB, MDCR_EL3.NSTBE, and MDCR_EL2.E2TB:
If EL3 is implemented, MDCR_EL3.NSTB is 0b0x, and either FEAT_RME is not implemented, or Secure state is implemented and MDCR_EL3.NSTBE is 0, then this field reads as one from:
Non-secure EL1 and Non-secure EL2.
If FEAT_RME is implemented, Realm EL1 and Realm EL2.
If Secure EL2 is implemented and enabled, and MDCR_EL2.E2TB is 0b00, Secure EL1.
If EL3 is implemented, MDCR_EL3.NSTB is 0b1x and either FEAT_RME is not implemented or MDCR_EL3.NSTBE is 0, then this field reads as one from:
If Secure state is implemented, Secure EL1.
If Secure EL2 is implemented, Secure EL2.
If EL2 is implemented and MDCR_EL2.E2TB is 0b00, Non-secure EL1.
If FEAT_RME is implemented, Realm EL1 and Realm EL2.
If FEAT_RME is implemented, and MDCR_EL3.{NSTB, NSTBE} is {0b1x, 1}, then this field reads as one from:
Non-secure EL1 and Non-secure EL2.
If Secure state is implemented, Secure EL1 and Secure EL2.
If MDCR_EL2.E2TB is 0b00, Realm EL1.
If EL3 is not implemented, EL2 is implemented, and MDCR_EL2.E2TB is 0b00, then this field reads as one from EL1.
Otherwise, this field reads as zero.
0b0
Programming is allowed.
0b1
Programming not allowed.
Align
3
0
3:0
Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.
All other values are reserved.
0b0000
Byte.
0b0001
Halfword.
0b0010
Word.
0b0011
Doubleword.
0b0100
16 bytes.
0b0101
32 bytes.
0b0110
64 bytes.
0b0111
128 bytes.
0b1000
256 bytes.
0b1001
512 bytes.
0b1010
1KB.
0b1011
2KB.
RO
MRS <Xt>, TRBIDR_EL1
if !IsFeatureImplemented(FEAT_TRBE) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRBIDR_EL1 == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
X{64}(t) = TRBIDR_EL1();
end;
elsif PSTATE.EL == EL2 then
if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
X{64}(t) = TRBIDR_EL1();
end;
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then
Halt(DebugHalt_SoftwareAccess);
else
X{64}(t) = TRBIDR_EL1();
end;
end;
2026-03-26 20:27:25
2026-03_rel