TRBLIMITR_EL1 Trace Buffer Limit Address Register when FEAT_TRBE is implemented TRBLIMITR_EL1 Architectural External 63 0 63 0 63 0 63 0 when FEAT_TRBE_EXT is implemented Defines the top address for the trace buffer, and controls the trace buffer modes and enable. TRBE TRBLIMITR_EL1 is a 64-bit register. LIMIT 63 12 63:12 Trace Buffer Limit pointer address. (TRBLIMITR_EL1.LIMIT << 12) is the address of the last byte in the trace buffer plus one. Bits [11:0] of the Limit pointer address are always zero. If the smallest implemented translation granule is not 4KB, then TRBLIMITR_EL1[N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value Log₂(smallest implemented translation granule). AU 11 7 11:7 Reserved, RES0. XE 6 6 0 Trace Buffer Unit External mode enable. Used for save/restore of TRBLIMITR_EL1.XE. Software must treat this field as UNK/SBZP when the OS Lock is unlocked. 0b0 Trace Buffer Unit is not enabled by this control. 0b1 If SelfHostedTraceEnabled() is FALSE, the Trace Buffer Unit is enabled. '0' When !OSLockStatus() RO RW When FEAT_TRBE_EXT is implemented 6 6 6 Reserved, RES0. Otherwise nVM 5 5 5 Address mode. If FEAT_TRBE_EXT is implemented and SelfHostedTraceEnabled() == FALSE, then the PE ignores the value of this field and the trace buffer pointers are always physical addresses. If FEAT_TRBEv1p1 is implemented, SelfHostedTraceEnabled() == TRUE, and the Effective value of TRFCR_EL2.DnVM is 1, then the PE ignores the value of this field, and the trace buffer pointers are always virtual addresses. 0b0 The trace buffer pointers are virtual addresses. 0b1 The trace buffer pointers are: Physical address in the owning security state if the owning translation regime has no stage 2 translation. Intermediate physical addresses in the owning security state if the owning translation regime has stage 2 translations. AU FEAT_TRBE_EXT is implemented !SelfHostedTraceEnabled() RES1 RW TM 4 3 4:3 Trigger mode. All other values are reserved. 0b00 Stop on trigger. Flush then stop collection and raise maintenance interrupt on Trigger Event. 0b01 IRQ on trigger. Continue collection and raise maintenance interrupt on Trigger Event. 0b11 Ignore trigger. Continue collection and do not raise maintenance interrupt on Trigger Event. AU FM 2 1 2:1 Trace buffer mode. All other values are reserved. 0b00 Fill mode. Stop collection and raise maintenance interrupt on current write pointer wrap. 0b01 Wrap mode. Continue collection and raise maintenance interrupt on current write pointer wrap. 0b11 Circular Buffer mode. Continue collection and do not raise maintenance interrupt on current write pointer wrap. AU E 0 0 0 Trace Buffer Unit enable. Controls whether the Trace Buffer Unit is enabled when SelfHostedTraceEnabled() == TRUE. If FEAT_TRBE_EXT is implemented and SelfHostedTraceEnabled() == FALSE, then TRBLIMITR_EL1.XE controls whether the Trace Buffer Unit is enabled. If FEAT_TRBE_EXT is not implemented, then the Trace Buffer Unit is disabled when SelfHostedTraceEnabled() == FALSE. All output is discarded by the Trace Buffer Unit when the Trace Buffer Unit is disabled. 0b0 Trace Buffer Unit is not enabled by this control. 0b1 If SelfHostedTraceEnabled() is TRUE, the Trace Buffer Unit is enabled. '0' The PE might ignore a write to TRBLIMITR_EL1 if all the following are true: TRBLIMITR_EL1.E is 1. Either FEAT_TRBE_EXT is not implemented or the Trace Buffer Unit is using Self-hosted mode. The write does not set TRBLIMITR_EL1.E to 0. If FEAT_TRBE_EXT is implemented, the PE might ignore a write to TRBLIMITR_EL1 if all the following are true: TRBLIMITR_EL1.XE is 1. The Trace Buffer Unit is using External mode. The write does not set TRBLIMITR_EL1.XE to 0. MRS <Xt>, TRBLIMITR_EL1 if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRBLIMITR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBLIMITR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBLIMITR_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBLIMITR_EL1(); end; end; MSR TRBLIMITR_EL1, <Xt> if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRBLIMITR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBLIMITR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBLIMITR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBLIMITR_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel