TRBMPAM_EL1 Trace Buffer MPAM Configuration Register when FEAT_TRBE_MPAM is implemented TRBMPAM_EL1 Architectural External 63 0 63 0 63 0 63 0 Defines the PARTID, PMG, and MPAM_SP values used by the trace buffer unit in external mode. TRBE TRBMPAM_EL1 is a 64-bit register. 63 27 63:27 Reserved, RES0. EN 26 26 26 Enable. Enables use of non-Default MPAM values. This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE. 0b0 Use Default physical PARTID and Default physical PMG values, and the PARTID space corresponding to the trace physical address space defined by TRBMAR_EL1.PAS. 0b1 Use TRBMPAM_EL1.{PARTID, PMG, MPAM_SP}. '0' MPAM_SP 25 24 25:24 Partition Identifier space. Selects the PARTID space. If the Trace Buffer Unit is using external mode and either TRBMPAM_EL1.MPAM_SP is set to reserved value, or the IMPLEMENTATION DEFINED authentication interface prohibits invasive debug of the Security state corresponding to the Partition Identifier space selected by TRBMPAM_EL1.MPAM_SP, then when the Trace Buffer Unit receives trace data from the trace unit, it does not write the trace data to memory and generates a trace buffer management event. The interface prohibits invasive debug of the Security state if any of the following apply: ExternalInvasiveDebugEnabled() == FALSE. Secure state is implemented, ExternalSecureInvasiveDebugEnabled() == FALSE and TRBMPAM_EL1.MPAM_SP is 0b00. FEAT_RME is implemented, ExternalRootInvasiveDebugEnabled() == FALSE, and TRBMPAM_EL1.MPAM_SP is 0b10. FEAT_RME is implemented, ExternalRealmInvasiveDebugEnabled() == FALSE, and TRBMPAM_EL1.MPAM_SP is 0b11. This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE. 0b00 PARTID is in the Secure PARTID space. When FEAT_Secure is implemented 0b01 PARTID is in the Non-secure PARTID space. 0b10 PARTID is in the Root PARTID space. When FEAT_RME is implemented 0b11 PARTID is in the Realm PARTID space. When FEAT_RME is implemented AU PMG 23 16 23:16 Performance Monitoring Group. Selects the PMG. Only sufficient low-order bits are required to represent the TRBDEVID1.PMG_MAX. Higher-order bits are RES0. This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE. AU PARTID 15 0 15:0 Partition Identifier. Selects the PARTID. Only sufficient low-order bits are required to represent the TRBDEVID1.PARTID_MAX. Higher-order bits are RES0. This field is ignored by the PE when SelfHostedTraceEnabled() == TRUE. AU The PE might ignore a write to TRBMPAM_EL1 if any of the following apply: TRBLIMITR_EL1.E is 1, and either FEAT_TRBE_EXT is not implemented or the Trace Buffer Unit is using Self-hosted mode. TRBLIMITR_EL1.XE is 1, FEAT_TRBE_EXT is implemented, and the Trace Buffer Unit is using External mode. MRS <Xt>, TRBMPAM_EL1 if !IsFeatureImplemented(FEAT_TRBE_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnTB2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nTRBMPAM_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBMPAM_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnTB2 == '0' then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBMPAM_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBMPAM_EL1(); end; end; MSR TRBMPAM_EL1, <Xt> if !IsFeatureImplemented(FEAT_TRBE_MPAM) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnTB2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nTRBMPAM_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMPAM_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnTB2 == '0' then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().EnTB2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMPAM_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBMPAM_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel