TRBSR_EL2 Trace Buffer Syndrome Register (EL2) when FEAT_TRBE_EXC is implemented Provides syndrome information to software for a trace buffer management event. TRBE If EL2 is not implemented, this register is RES0 from EL3. TRBSR_EL2 is a 64-bit register. 63 56 63:56 Reserved, RES0. MSS2 55 32 55:32 Management event Specific Syndrome 2. Contains syndrome specific to the management event. The syndrome contents for each management event are described in the following sections. other trace buffer management events 23 0 23:0 Reserved, RES0. stage 1 or stage 2 Data Aborts on write to trace buffer 23 9 23:9 Reserved, RES0. TopLevel 8 8 0 TopLevel. Indicates if the fault was due to TopLevel. 0b0 Fault is not due to TopLevel. 0b1 Fault is due to TopLevel. When FEAT_THE is implemented 8 8 8 Reserved, RES0. Otherwise AssuredOnly 7 7 0 AssuredOnly flag. If a memory access generates a stage 2 Data Abort, then this field holds information about the fault. 0b0 Data Abort is not due to AssuredOnly. 0b1 Data Abort is due to AssuredOnly. When FEAT_THE is implemented, TRBSR_EL2.EC == '100101', and GetTRBSR_EL2_FSC() IN {'0011xx'} 7 7 7 Reserved, RES0. Otherwise Overlay 6 6 0 Overlay flag. If a memory access generates a Data Abort for a Permission fault, then this field holds information about the fault. 0b0 Data Abort is not due to Overlay Permissions. 0b1 Data Abort is due to Overlay Permissions. When (FEAT_S1POE is implemented or FEAT_S2POE is implemented) and GetTRBSR_EL2_FSC() IN {'0011xx'} 6 6 6 Reserved, RES0. Otherwise DirtyBit 5 5 0 DirtyBit flag. If a write access to memory generates a Data Abort for a Permission fault using Indirect Permission, then this field holds information about the fault. 0b0 Permission Fault is not due to dirty state. 0b1 Permission Fault is due to dirty state. When (FEAT_S1PIE is implemented or FEAT_S2PIE is implemented) and GetTRBSR_EL2_FSC() IN {'0011xx'} 5 5 5 Reserved, RES0. Otherwise 4 0 4:0 Reserved, RES0. When FEAT_RME is implemented Granule Protection Check faults on write to trace buffer 23 0 23:0 Reserved, RES0. When FEAT_RME is implemented trace buffer management event for an IMPLEMENTATION DEFINED reason IMPLEMENTATION DEFINED 23 0 23:0 IMPLEMENTATION DEFINED. EC 31 26 31:26 Event class. Top-level description of the cause of the trace buffer management event. All other values are reserved. 0b000000 Other trace buffer management event. All trace buffer management events other than those described by the other defined Event class codes. 0b011110 Granule Protection Check fault on write to trace buffer, other than Granule Protection Fault (GPF). That is, any of the following: Granule Protection Table (GPT) address size fault. GPT walk fault. External abort on GPT fetch. A GPF on translation table walk or update is reported as either a Stage 1 or Stage 2 Data Abort, as appropriate. Other GPFs are reported as a Stage 1 Data Abort. When FEAT_RME is implemented 0b011111 Trace buffer management event for an IMPLEMENTATION DEFINED reason. 0b100100 Stage 1 Data Abort on write to trace buffer. 0b100101 Stage 2 Data Abort on write to trace buffer. AU 25 23 25:23 Reserved, RES0. IRQ 22 22 22 Maintenance status. Indicates that a trace buffer management event has been recorded. When FEAT_TRBE_EXC is implemented, this field indicates a management event for EL2. If the TRBE Profiling exception for EL2 is enabled, then when this field is 1, a TRBE Profiling exception for EL2 is pending 0b0 No trace buffer management event for EL2 has been recorded. 0b1 A trace buffer management event for EL2 has been recorded. AU TRG 21 21 21 Triggered. 0b0 No Detected Trigger has been observed since this field was last cleared to zero. 0b1 A Detected Trigger has been observed since this field was last cleared to zero. AU WRAP 20 20 20 Wrapped. For each byte of trace the Trace Buffer Unit Accepts and writes to the trace buffer at the address in the current write pointer, if the current write pointer is equal to the Limit pointer minus one, the current write pointer is wrapped by setting it to the Base pointer, and this field is set to 1. 0b0 The current write pointer has not wrapped since this field was last cleared to zero. 0b1 The current write pointer has wrapped since this field was last cleared to zero. AU 19 19 19 Reserved, RES0. EA 18 18 0 External Abort. It is IMPLEMENTATION DEFINED whether this field is set to 1 or is unchanged by the PE when a write by the Trace Buffer Unit generates an External abort on a translation table walk, translation table update, or GPT walk that is reported as an MMU fault. From Armv9.3, this field is not set to 1 by the PE for any other trace buffer management event. 0b0 An External abort has not been asserted. 0b1 An External abort has been asserted and detected by the Trace Buffer Unit. AU When the PE sets this bit as the result of an External abort 18 18 18 Reserved, RES0. Otherwise S 17 17 17 Stopped. 0b0 Collection has not been stopped. 0b1 Collection is stopped. AU 16 16 16 Reserved, RES0. MSS 15 0 15:0 Management Event Specific Syndrome. Contains syndrome specific to the trace buffer management event. The syndrome contents for each trace buffer management event are described in the following sections. other trace buffer management events 15 6 15:6 Reserved, RES0. BSC 5 0 5:0 Trace buffer status code All other values are reserved. 0b000000 Collection not stopped, or access not allowed. 0b000001 Trace buffer filled. Collection stopped because the current write pointer wrapped to the base pointer and the trace buffer mode is Fill mode. 0b000010 Trigger Event. Collection stopped because of a Trigger Event. See TRBTRG_EL1 for more information. 0b000011 Manual Stop. Collection stopped because of a Manual Stop event. See TRBCR.ManStop for more information. When FEAT_TRBE_EXT is implemented 0b000100 Buffer size. The requested trace buffer size was too large. stage 1 or stage 2 Data Aborts on write to trace buffer 15 6 15:6 Reserved, RES0. FSC 5 0 5:0 Fault status code All other values are reserved. 0b000000 Address size fault, level 0 of translation or translation table base register. 0b000001 Address size fault, level 1. 0b000010 Address size fault, level 2. 0b000011 Address size fault, level 3. 0b000100 Translation fault, level 0. 0b000101 Translation fault, level 1. 0b000110 Translation fault, level 2. 0b000111 Translation fault, level 3. 0b001001 Access flag fault, level 1. 0b001010 Access flag fault, level 2. 0b001011 Access flag fault, level 3. 0b001000 Access flag fault, level 0. When FEAT_LPA2 is implemented 0b001100 Permission fault, level 0. When FEAT_LPA2 is implemented 0b001101 Permission fault, level 1. 0b001110 Permission fault, level 2. 0b001111 Permission fault, level 3. 0b010000 Synchronous External abort, not on translation table walk or hardware update of translation table. 0b010001 Asynchronous External abort. 0b010010 Synchronous External abort on translation table walk or hardware update of translation table, level -2. When FEAT_D128 is implemented 0b010011 Synchronous External abort on translation table walk or hardware update of translation table, level -1. When FEAT_LPA2 is implemented 0b010100 Synchronous External abort on translation table walk or hardware update of translation table, level 0. 0b010101 Synchronous External abort on translation table walk or hardware update of translation table, level 1. 0b010110 Synchronous External abort on translation table walk or hardware update of translation table, level 2. 0b010111 Synchronous External abort on translation table walk or hardware update of translation table, level 3. 0b011011 Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1. When FEAT_LPA2 is implemented and FEAT_RAS is not implemented 0b100001 Alignment fault. 0b100010 Granule Protection Fault on translation table walk or hardware update of translation table, level -2. When FEAT_D128 is implemented and FEAT_RME is implemented 0b100011 Granule Protection Fault on translation table walk or hardware update of translation table, level -1. When FEAT_RME is implemented and FEAT_LPA2 is implemented 0b100100 Granule Protection Fault on translation table walk or hardware update of translation table, level 0. When FEAT_RME is implemented 0b100101 Granule Protection Fault on translation table walk or hardware update of translation table, level 1. When FEAT_RME is implemented 0b100110 Granule Protection Fault on translation table walk or hardware update of translation table, level 2. When FEAT_RME is implemented 0b100111 Granule Protection Fault on translation table walk or hardware update of translation table, level 3. When FEAT_RME is implemented 0b101000 Granule Protection Fault, not on translation table walk or hardware update of translation table. When FEAT_RME is implemented 0b101001 Address size fault, level -1. When FEAT_LPA2 is implemented 0b101010 Translation fault, level -2. When FEAT_D128 is implemented 0b101011 Translation fault, level -1. When FEAT_LPA2 is implemented 0b101100 Address Size fault, level -2. When FEAT_D128 is implemented 0b110000 TLB conflict abort. 0b110001 Unsupported atomic hardware update fault. When FEAT_HAF is implemented AU When FEAT_RME is implemented Granule Protection Check faults on write to trace buffer 15 0 15:0 Reserved, RES0. When FEAT_RME is implemented trace buffer management event for an IMPLEMENTATION DEFINED reason IMPLEMENTATION DEFINED 15 0 15:0 IMPLEMENTATION DEFINED. The PE might ignore a write to TRBSR_EL2 if any of the following apply: TRBLIMITR_EL1.E is 1, and either FEAT_TRBE_EXT is not implemented or the Trace Buffer Unit is using Self-hosted mode. TRBLIMITR_EL1.XE is 1, FEAT_TRBE_EXT is implemented, and the Trace Buffer Unit is using External mode. When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the accessor name TRBSR_EL2 or TRBSR_EL1 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, TRBSR_EL2 if !IsFeatureImplemented(FEAT_TRBE_EXC) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TRBEE == '00' then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TRBEE == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = TRBSR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = TRBSR_EL2(); end; MSR TRBSR_EL2, <Xt> if !IsFeatureImplemented(FEAT_TRBE_EXC) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TRBEE == '00' then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && MDCR_EL3().TRBEE == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else TRBSR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then TRBSR_EL2() = X{64}(t); end; MRS <Xt>, TRBSR_EL1 if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRBSR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} && (EffectiveTRFCR_EL2_EE() != '00' && TRFCR_EL1().EE != '00') then X{64}(t) = NVMem(0x860); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBSR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); elsif EffectiveTRFCR_EL2_EE() != '00' && ELIsInHost(EL2) then X{64}(t) = TRBSR_EL2(); else X{64}(t) = TRBSR_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBSR_EL1(); end; end; MSR TRBSR_EL1, <Xt> if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRBSR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} && (EffectiveTRFCR_EL2_EE() != '00' && TRFCR_EL1().EE != '00') then NVMem(0x860) = X{64}(t); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); elsif EffectiveTRFCR_EL2_EE() != '00' && ELIsInHost(EL2) then TRBSR_EL2() = X{64}(t); else TRBSR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBSR_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel