TRBTRG_EL1 Trace Buffer Trigger Counter Register when FEAT_TRBE is implemented TRBTRG_EL1 Architectural External 63 0 63 0 63 0 63 0 when FEAT_TRBE_EXT is implemented Specifies the number of bytes of trace to capture following a Detected Trigger before a Trigger Event. TRBE TRBTRG_EL1 is a 64-bit register. 63 32 63:32 Reserved, RES0. TRG 31 0 31:0 Trigger count. Specifies the number of bytes of trace to capture following a Detected Trigger before a Trigger Event. TRBTRG_EL1 decrements by 1 for every byte of trace written to the trace buffer when all of the following are true: TRBTRG_EL1 is nonzero. TRBSR_EL1.TRG is 1. The architecture places restrictions on the values that software can write to the counter. As a result of the restrictions an implementation might treat some of TRG[M:0] as RES0, where M is defined by TRBIDR_EL1.Align. AU The PE might ignore a write to TRBTRG_EL1 if any of the following apply: TRBLIMITR_EL1.E is 1, and either FEAT_TRBE_EXT is not implemented or the Trace Buffer Unit is using Self-hosted mode. TRBLIMITR_EL1.XE is 1, FEAT_TRBE_EXT is implemented, and the Trace Buffer Unit is using External mode. MRS <Xt>, TRBTRG_EL1 if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRBTRG_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBTRG_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBTRG_EL1(); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRBTRG_EL1(); end; end; MSR TRBTRG_EL1, <Xt> if !IsFeatureImplemented(FEAT_TRBE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRBTRG_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().E2TB IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBTRG_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSTBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSTBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBTRG_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRBTRG_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel