TRCACATR<n> Trace Address Comparator Access Type Register <n> when FEAT_ETE is implemented, System register access to the trace unit registers is implemented, and UInt(TRCIDR4.NUMACPAIRS) * 2 > n 0 15 TRCACATR<n> Architectural External 63 0 63 0 63 0 63 0 Defines the type of access for the corresponding TRCACVR<n> Register. This register configures the context type, Exception levels, alignment, masking that is applied by the Address Comparator, and how the Address Comparator behaves when it is one half of an Address Range Comparator. Trace TRCACATR<n> is a 64-bit register. 63 19 63:19 Reserved, RES0. EXLEVEL_RL_EL2 18 18 0 Realm EL2 address comparison control. Controls whether a comparison can occur at EL2 in Realm state. 0b0 When TRCACATR<n>.EXLEVEL_NS_EL2 is 0 the Address Comparator performs comparisons in Realm EL2. When TRCACATR<n>.EXLEVEL_NS_EL2 is 1 the Address Comparator does not perform comparisons in Realm EL2. 0b1 When TRCACATR<n>.EXLEVEL_NS_EL2 is 0 the Address Comparator does not perform comparisons in Realm EL2. When TRCACATR<n>.EXLEVEL_NS_EL2 is 1 the Address Comparator performs comparisons in Realm EL2. AU When FEAT_RME is implemented 18 18 18 Reserved, RES0. Otherwise EXLEVEL_RL_EL1 17 17 0 Realm EL1 address comparison control. Controls whether a comparison can occur at EL1 in Realm state. 0b0 When TRCACATR<n>.EXLEVEL_NS_EL1 is 0 the Address Comparator performs comparisons in Realm EL1. When TRCACATR<n>.EXLEVEL_NS_EL1 is 1 the Address Comparator does not perform comparisons in Realm EL1. 0b1 When TRCACATR<n>.EXLEVEL_NS_EL1 is 0 the Address Comparator does not perform comparisons in Realm EL1. When TRCACATR<n>.EXLEVEL_NS_EL1 is 1 the Address Comparator performs comparisons in Realm EL1. AU When FEAT_RME is implemented 17 17 17 Reserved, RES0. Otherwise EXLEVEL_RL_EL0 16 16 0 Realm EL0 address comparison control. Controls whether a comparison can occur at EL0 in Realm state. 0b0 When TRCACATR<n>.EXLEVEL_NS_EL0 is 0 the Address Comparator performs comparisons in Realm EL0. When TRCACATR<n>.EXLEVEL_NS_EL0 is 1 the Address Comparator does not perform comparisons in Realm EL0. 0b1 When TRCACATR<n>.EXLEVEL_NS_EL0 is 0 the Address Comparator does not perform comparisons in Realm EL0. When TRCACATR<n>.EXLEVEL_NS_EL0 is 1 the Address Comparator performs comparisons in Realm EL0. AU When FEAT_RME is implemented 16 16 16 Reserved, RES0. Otherwise 15 15 15 Reserved, RES0. EXLEVEL_NS_EL2 14 14 0 Non-secure EL2 address comparison control. Controls whether a comparison can occur at EL2 in Non-secure state. 0b0 The Address Comparator performs comparisons in Non-secure EL2. 0b1 The Address Comparator does not perform comparisons in Non-secure EL2. AU When Non-secure EL2 is implemented 14 14 14 Reserved, RES0. Otherwise EXLEVEL_NS_EL1 13 13 0 Non-secure EL1 address comparison control. Controls whether a comparison can occur at EL1 in Non-secure state. 0b0 The Address Comparator performs comparisons in Non-secure EL1. 0b1 The Address Comparator does not perform comparisons in Non-secure EL1. AU When Non-secure EL1 is implemented 13 13 13 Reserved, RES0. Otherwise EXLEVEL_NS_EL0 12 12 0 Non-secure EL0 address comparison control. Controls whether a comparison can occur at EL0 in Non-secure state. 0b0 The Address Comparator performs comparisons in Non-secure EL0. 0b1 The Address Comparator does not perform comparisons in Non-secure EL0. AU When Non-secure EL0 is implemented 12 12 12 Reserved, RES0. Otherwise EXLEVEL_S_EL3 11 11 0 EL3 address comparison control. Controls whether a comparison can occur at EL3. 0b0 The Address Comparator performs comparisons at EL3. 0b1 The Address Comparator does not perform comparisons at EL3. AU When EL3 is implemented 11 11 11 Reserved, RES0. Otherwise EXLEVEL_S_EL2 10 10 0 Secure EL2 address comparison control. Controls whether a comparison can occur at EL2 in Secure state. 0b0 The Address Comparator performs comparisons in Secure EL2. 0b1 The Address Comparator does not perform comparisons in Secure EL2. AU When Secure EL2 is implemented 10 10 10 Reserved, RES0. Otherwise EXLEVEL_S_EL1 9 9 0 Secure EL1 address comparison control. Controls whether a comparison can occur at EL1 in Secure state. 0b0 The Address Comparator performs comparisons in Secure EL1. 0b1 The Address Comparator does not perform comparisons in Secure EL1. AU When Secure EL1 is implemented 9 9 9 Reserved, RES0. Otherwise EXLEVEL_S_EL0 8 8 0 Secure EL0 address comparison control. Controls whether a comparison can occur at EL0 in Secure state. 0b0 The Address Comparator performs comparisons in Secure EL0. 0b1 The Address Comparator does not perform comparisons in Secure EL0. AU When Secure EL0 is implemented 8 8 8 Reserved, RES0. Otherwise 7 7 7 Reserved, RES0. CONTEXT 6 4 2:0 Selects a Context Identifier Comparator or Virtual Context Identifier Comparator: The width of this field is dependent on the maximum number of Context Identifier Comparators or Virtual Context Identifier Comparators implemented. Unimplemented bits are RES0. 0b000 Comparator 0. 0b001 Comparator 1. When UInt(TRCIDR4.NUMCIDC) > 1 or UInt(TRCIDR4.NUMVMIDC) > 1 0b010 Comparator 2. When UInt(TRCIDR4.NUMCIDC) > 2 or UInt(TRCIDR4.NUMVMIDC) > 2 0b011 Comparator 3. When UInt(TRCIDR4.NUMCIDC) > 3 or UInt(TRCIDR4.NUMVMIDC) > 3 0b100 Comparator 4. When UInt(TRCIDR4.NUMCIDC) > 4 or UInt(TRCIDR4.NUMVMIDC) > 4 0b101 Comparator 5. When UInt(TRCIDR4.NUMCIDC) > 5 or UInt(TRCIDR4.NUMVMIDC) > 5 0b110 Comparator 6. When UInt(TRCIDR4.NUMCIDC) > 6 or UInt(TRCIDR4.NUMVMIDC) > 6 0b111 Comparator 7. When UInt(TRCIDR4.NUMCIDC) > 7 or UInt(TRCIDR4.NUMVMIDC) > 7 AU When TRCIDR4.NUMCIDC != '0000' or TRCIDR4.NUMVMIDC != '0000' 6 4 6:4 Reserved, RES0. Otherwise CONTEXTTYPE 3 2 1:0 Controls whether the Address Comparator is dependent on a Context Identifier Comparator, a Virtual Context Identifier Comparator, or both comparisons. If TRCIDR4.NUMCIDC == 0b0000, then bit [2] is RES0. If TRCIDR4.NUMVMIDC == 0b0000, then bit [3] is RES0. 0b00 The Address Comparator is not dependent on the Context Identifier Comparators or Virtual Context Identifier Comparators. 0b01 The Address Comparator is dependent on the Context Identifier Comparator that TRCACATR<n>.CONTEXT specifies. The Address Comparator signals a match only if both the Context Identifier Comparator and the address comparison match. When TRCIDR4.NUMCIDC != '0000' 0b10 The Address Comparator is dependent on the Virtual Context Identifier Comparator that TRCACATR<n>.CONTEXT specifies. The Address Comparator signals a match only if both the Virtual Context Identifier Comparator and the address comparison match. When TRCIDR4.NUMVMIDC != '0000' 0b11 The Address Comparator is dependent on the Context Identifier Comparator and Virtual Context Identifier Comparator that TRCACATR<n>.CONTEXT specifies. The Address Comparator signals a match only if the Context Identifier Comparator, the Virtual Context Identifier Comparator, and address comparison all match. When TRCIDR4.NUMCIDC != '0000' and TRCIDR4.NUMVMIDC != '0000' AU When TRCIDR4.NUMCIDC != '0000' or TRCIDR4.NUMVMIDC != '0000' 3 2 3:2 Reserved, RES0. Otherwise 1 0 1:0 Reserved, RES0. Must be programmed if any of the following are true: TRCBBCTLR.RANGE[n/2] == 1. TRCRSCTLR<a>.GROUP == 0b0100 and TRCRSCTLR<a>.SAC[n] == 1. TRCRSCTLR<a>.GROUP == 0b0101 and TRCRSCTLR<a>.ARC[n/2] == 1. TRCVIIECTLR.EXCLUDE[n/2] == 1. TRCVIIECTLR.INCLUDE[n/2] == 1. TRCVISSCTLR.START[n] == 1. TRCVISSCTLR.STOP[n] == 1. TRCSSCCR<>.ARC[n/2] == 1. TRCSSCCR<>.SAC[n] == 1. TRCQCTLR.RANGE[n/2] == 1. Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state. 0-15 MRS <Xt>, TRCACATR<m> let m:integer = UInt(op2[0] :: CRm[3:1]); if m >= NUM_TRACE_ADDRESS_COMPARATOR_PAIRS * 2 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCACATR(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCACATR(m); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCACATR(m); end; end; 0-15 MSR TRCACATR<m>, <Xt> let m:integer = UInt(op2[0] :: CRm[3:1]); if m >= NUM_TRACE_ADDRESS_COMPARATOR_PAIRS * 2 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().TRC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCACATR(m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCACATR(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else TRCACATR(m) = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel