TRCIDR0 Trace ID Register 0 when FEAT_ETE is implemented and System register access to the trace unit registers is implemented TRCIDR0 Architectural External 31 0 31 0 31 0 31 0 Returns the tracing capabilities of the trace unit. Identification Registers TRCIDR0 is a 64-bit register. 63 31 63:31 Reserved, RES0. COMMTRANS 30 30 30 Transaction Start element behavior. 0b0 Transaction Start elements are P0 elements. 0b1 Transaction Start elements are not P0 elements. RO COMMOPT 29 29 29 Indicates the contents and encodings of Cycle count packets. The Commit mode defines the contents and encodings of Cycle Count packets, in particular how Commit elements are indicated by these packets. See the descriptions of these packets for more details. 0b0 Commit mode 0. 0b1 Commit mode 1. TRCIDR0.TRCCCI == '1' UInt(TRCIDR8.MAXSPEC) == 0x0 RAO/WI When TRCIDR0.TRCCCI == '0' RAZ/WI RO TSSIZE 28 24 28:24 Indicates that the trace unit implements Global timestamping and the size of the timestamp value. All other values are reserved. This field reads as 0b01000. 0b00000 Global timestamping not implemented. 0b01000 Global timestamping implemented with a 64-bit timestamp value. RO TSMARK 23 23 23 Indicates whether Timestamp Marker elements are generated. 0b0 Timestamp Marker elements are not generated. 0b1 Timestamp Marker elements are generated. RO ITE 22 22 22 Indicates whether Instrumentation Trace is implemented. This field has the value 1 if FEAT_ITE is implemented. 0b0 Instrumentation Trace not implemented. 0b1 Instrumentation Trace implemented. RO 21 18 21:18 Reserved, RES0. TRCEXDATA 17 17 0 Indicates if the trace unit implements tracing of data transfers for exceptions and exception returns. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures. 0b0 Tracing of data transfers for exceptions and exception returns not implemented. 0b1 Tracing of data transfers for exceptions and exception returns implemented. RO When TRCIDR0.TRCDATA != '00' 17 17 17 Reserved, RES0. Otherwise QSUPP 16 15 16:15 Indicates that the trace unit implements Q element support. 0b00 Q element support is not implemented. 0b01 Q element support is implemented, and only supports Q elements with instruction counts. 0b10 Q element support is implemented, and only supports Q elements without instruction counts. 0b11 Q element support is implemented, and supports: Q elements with instruction counts. Q elements without instruction counts. RO QFILT 14 14 14 Indicates if the trace unit implements Q element filtering. If TRCIDR0.QSUPP == 0b00 then this field is 0. 0b0 Q element filtering is not implemented. 0b1 Q element filtering is implemented. RO CONDTYPE 13 12 1:0 Indicates how conditional instructions are traced. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures. All other values are reserved. 0b00 Conditional instructions are traced with an indication of whether they pass or fail their condition code check. 0b01 Conditional instructions are traced with an indication of the APSR condition flags. RO When TRCIDR0.TRCCOND == '1' 13 12 13:12 Reserved, RES0. Otherwise NUMEVENT 11 10 1:0 Indicates the number of ETEEvents implemented. All other values are reserved. 0b00 The trace unit supports 0 ETEEvents. RO When TRCIDR4.NUMRSPAIR == '0000' NUMEVENT 11 10 1:0 Indicates the number of ETEEvents implemented. 0b00 The trace unit supports 1 ETEEvent. 0b01 The trace unit supports 2 ETEEvents. 0b10 The trace unit supports 3 ETEEvents. 0b11 The trace unit supports 4 ETEEvents. RO When TRCIDR4.NUMRSPAIR != '0000' 11 10 11:10 Reserved, RES0. Otherwise RETSTACK 9 9 9 Indicates if the trace unit supports the return stack. 0b0 Return stack not implemented. 0b1 Return stack implemented. RO 8 8 8 Reserved, RES0. TRCCCI 7 7 7 Indicates if the trace unit implements cycle counting. This field reads as 1. 0b0 Cycle counting not implemented. 0b1 Cycle counting implemented. RO TRCCOND 6 6 6 Indicates if the trace unit implements conditional instruction tracing. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures. This field reads as 0. 0b0 Conditional instruction tracing not implemented. 0b1 Conditional instruction tracing implemented. RO TRCBB 5 5 5 Indicates if the trace unit implements branch broadcasting. This field reads as 1. 0b0 Branch broadcasting not implemented. 0b1 Branch broadcasting implemented. RO TRCDATA 4 3 4:3 Indicates if the trace unit implements data tracing. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. All other values are reserved. This field reads as 0b00. 0b00 Data tracing not implemented. 0b11 Data tracing implemented. RO INSTP0 2 1 2:1 Indicates if load and store instructions are P0 instructions. Load and store instructions as P0 instructions is not implemented in ETE and this field is reserved for other trace architectures. All other values are reserved. When FEAT_ETE is implemented, the only permitted value is 0b00. 0b00 Load and store instructions are not P0 instructions. 0b11 Load and store instructions are P0 instructions. RO 0 0 0 Reserved, RES1. MRS <Xt>, TRCIDR0 if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRCID == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR0(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR0(); end; end; 2026-03-26 20:27:25 2026-03_rel