TRCIDR3 Trace ID Register 3 when FEAT_ETE is implemented and System register access to the trace unit registers is implemented TRCIDR3 Architectural External 31 0 31 0 31 0 31 0 Returns the base architecture of the trace unit. Trace TRCIDR3 is a 64-bit register. 63 32 63:32 Reserved, RES0. NOOVERFLOW 31 31 31 Indicates if overflow prevention is implemented. If TRCIDR3.STALLCTL == 0 then this field is 0. 0b0 Overflow prevention is not implemented. 0b1 Overflow prevention is implemented. RO NUMPROC 30 28 13:12, 30:28 Indicates the number of PEs available for tracing. This field reads as 0b00000. The NUMPROC field is split as follows: NUMPROC[2:0] is TRCIDR3[30:28]. NUMPROC[4:3] is TRCIDR3[13:12]. 13 12 30 28 NUMPROC 0b00000 The trace unit can trace one PE. RO SYSSTALL 27 27 27 Indicates if stalling of the PE is permitted. The value of this field might be dynamic and change based on system conditions. If TRCIDR3.STALLCTL == 0 then this field is 0. 0b0 Stalling of the PE is not permitted. 0b1 Stalling of the PE is permitted. RO STALLCTL 26 26 26 Indicates if trace unit implements stalling of the PE. 0b0 Stalling of the PE is not implemented. 0b1 Stalling of the PE is implemented. RO SYNCPR 25 25 25 Indicates if an implementation has a fixed synchronization period. This field reads as 0. 0b0 TRCSYNCPR is read/write so software can change the synchronization period. 0b1 TRCSYNCPR is read-only so the synchronization period is fixed. RO TRCERR 24 24 24 Indicates forced tracing of System Error exceptions is implemented. This field reads as 1. 0b0 Forced tracing of System Error exceptions is not implemented. 0b1 Forced tracing of System Error exceptions is implemented. RO 23 23 23 Reserved, RES0. EXLEVEL_NS_EL2 22 22 22 Indicates if Non-secure EL2 is implemented. 0b0 Non-secure EL2 is not implemented. 0b1 Non-secure EL2 is implemented. RO EXLEVEL_NS_EL1 21 21 21 Indicates if Non-secure EL1 is implemented. 0b0 Non-secure EL1 is not implemented. 0b1 Non-secure EL1 is implemented. RO EXLEVEL_NS_EL0 20 20 20 Indicates if Non-secure EL0 is implemented. 0b0 Non-secure EL0 is not implemented. 0b1 Non-secure EL0 is implemented. RO EXLEVEL_S_EL3 19 19 19 Indicates if EL3 is implemented. 0b0 EL3 is not implemented. 0b1 EL3 is implemented. RO EXLEVEL_S_EL2 18 18 18 Indicates if Secure EL2 is implemented. 0b0 Secure EL2 is not implemented. 0b1 Secure EL2 is implemented. RO EXLEVEL_S_EL1 17 17 17 Indicates if Secure EL1 is implemented. 0b0 Secure EL1 is not implemented. 0b1 Secure EL1 is implemented. RO EXLEVEL_S_EL0 16 16 16 Indicates if Secure EL0 is implemented. 0b0 Secure EL0 is not implemented. 0b1 Secure EL0 is implemented. RO 15 14 15:14 Reserved, RES0. NUMPROC[4:3] 13 12 13:12, 30:28 This field is bits[4:3] of NUMPROC[4:0]. See NUMPROC[2:0] for the field description. CCITMIN 11 0 11:0 Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD. Reads as 0x000. RO When TRCIDR0.TRCCCI == '0' CCITMIN 11 0 11:0 Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD. The minimum value of this field is 0x001. 0x001..0xFFF The minimum value that can be programmed in TRCCCCTLR.THRESHOLD. RO When TRCIDR0.TRCCCI == '1' 11 0 11:0 Reserved, RES0. Otherwise MRS <Xt>, TRCIDR3 if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRCID == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR3(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR3(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCIDR3(); end; end; 2026-03-26 20:27:25 2026-03_rel