TRCOSLSR Trace OS Lock Status Register when FEAT_ETE is implemented and System register access to the trace unit registers is implemented TRCOSLSR Architectural External 31 0 31 0 31 0 31 0 Returns the status of the Trace OS Lock. Trace Management TRCOSLSR is a 64-bit register. 63 5 63:5 Reserved, RES0. OSLM 4 3 4:3, 0 OS Lock model. All other values are reserved. When FEAT_ETE is implemented, the values 0b000 and 0b010 are not permitted. The OSLM field is split as follows: OSLM[2:1] is TRCOSLSR[4:3]. OSLM[0] is TRCOSLSR[0]. 4 3 0 0 OSLM 0b000 Trace OS Lock is not implemented. 0b010 Trace OS Lock is implemented. 0b100 Trace OS Lock is not implemented, and the trace unit is controlled by the PE OS Lock. RO 2 2 2 Reserved, RES0. OSLK 1 1 1 OS Lock status. When FEAT_ETE is implemented, this field indicates the state of the PE OS Lock. When FEAT_ETMv4 is implemented, this field indicates the state of the Trace OS Lock. 0b0 The OS Lock is unlocked. 0b1 The OS Lock is locked. OSLM[0] 0 0 4:3, 0 This field is bit[0] of OSLM[2:0]. See OSLM[2:1] for the field description. MRS <Xt>, TRCOSLSR if !(IsFeatureImplemented(FEAT_ETE) && IsFeatureImplemented(FEAT_TRC_SR)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPACR_EL1().TTA == '1' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().TRCOSLSR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCOSLSR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TTA == '1' then Undefined(); elsif CPTR_EL2().TTA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TTA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCOSLSR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TTA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR2().TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X{64}(t) = TRCOSLSR(); end; end; 2026-03-26 20:27:25 2026-03_rel